PORTLAND, Ore. — Samsung is funding Pennsylvania State University researchers working to fabricate III-V indium gallium arsenide FinFETs for possible use at the 7nm node.
The silicon FinFET (3D fin gates on field effect transistors) have become the standard for low leakage and high performance at advanced nodes, but III-V compounds such as indium gallium arsenide (InGaAs) are faster than silicon, prompting researchers at Penn State to combine the best of both worlds. Penn State's InGaAs FinFET transistors use a novel five-gate structure grown on an indium phosphide (InP) substrate in its Materials Research Institute's Nanofabrication Laboratory.
"These FinFETs as of now have been fabricated on InP substrates," Arun Thathachary, a EE doctoral candidate working under professor Suman Datta, told us. "Samsung will own the IP generated from this project." Fellow doctoral candidate Nidhi Agrawal has also contributed to the project.
For years, other semiconductor firms have funded research to fabricate III-V transistors on silicon substrates, including Intel, Sematech, and, more recently, Imec.
The reason everybody is trying to integrate III-V transistor channels with silicon substrates is cost. Not only are InP wafers more expensive, but the entire semiconductor industry is based on equipment optimized for silicon manufacturing. So even though Penn State is using InP wafers to prove the concept that III-V FinFETs will retain their high mobility at advanced nodes (5 nm) and at lower voltages (0.5 V), Samsung would eventually have to solve the problems of integrating III-V materials with complementary (n- and p-channel) metal-oxide semiconductors (CMOS) on 12-inch (300mm) silicon substrates.
Scanning electron microscope micrograph of a multigate indium gallium arsenide (InGaAs) field effect transistor using an array of five
(Source: Penn State)
Thathachary told EE us:
This entire research project is being sponsored by Samsung with the sole purpose of investigating III-V materials for low-power CMOS manufacturing. But as far as integration on 300-millimeter silicon goes, there are significant growth challenges involved in engineering the buffer layers. Though there have been several publications in this regard over the last couple of years, a high-yield solution for 300-millimeter manufacturing is still lacking. Additionally, III-V materials only provide excellent electron mobility, which means n-channel only. For p-channel devices, there is a significant effort in co-integrating germanium channels alongside III-V to facilitate 300-millimeter CMOS manufacturing. This is also being actively investigated by several companies and consortia, including Imec and Sematech.