The I6400 has the option of adding up to four threads to the core to match the application requirements.
Our previous generations that have MT had one pipeline with multiple threads and used the threading to keep the pipeline full with dual-instruction issue. With this, the number of threads is optional, but it always has the dual pipeline. If someone really wants the single-pipeline multithreaded version, we have interAptiv already, so this isn't a complete replacement. It takes the range to a new level and brings 64 bits into the equation.
Preliminary benchmarking shows that adding a second thread leads to performance increases of 40-60% on popular industry benchmarks, including SPECint and EEMBC's CoreMark, Imagination said in a press release. This comes with a cluster area increase of less than 10% -- 1 mm2 @ 1 GHz with 5.6 CoreMark/MHz and 3.0 DMIPS/MHz. However, the power figure (the key metric for multithreading) has yet to be determined.
"We believe, based on the current power data that, we are getting competitive with competitive offerings," Throndson said. "Power tracks with area, certainly with leakage," though some of this advantage may come from being able to shut down more of the cores with the Power Gearing technology. This includes the ability to provide a dedicated clock and voltage level to each core in a heterogeneous cluster while maintaining coherency across CPUs, so that sleeping cores wake only when needed.
"This was designed to be a 64-bit processor, but because of the target we achieved with the core, we believe it still fits well in the 32-bit processors for performance, footprint, and power consumption," he said. "The overhead of going to 64 bits is minimized, as MIPS64 is a proper superset of MIPS32, adding 64 instructions so you can run existing MIPS32 software without mode switching."
With the hardware virtualization support, the I6400 includes support for up to 15 secure/nonsecure guests. It supports multiple independent security contexts and multiple independent execution domains. This uses technology from Imagination and its ecosystem partners and can encompass other critical components of an SoC to support simultaneous secure content delivery, secure payments, identity protection, and more across multiple applications and content sources.
The hardware floating point unit (FPU) in the I6400 supports both single and double precision capabilities, which are relevant to general computing and control systems processing. The instructions for the 128-bit SIMD engine are defined to be supported within high-level languages such as C or OpenCL. The SIMD in the I6400 supports a wide variety of integer (8, 16, 32, and 64-bit) and floating point (32, 64-bit) data types. Imagination said in the release that this feature makes the produce "highly efficient for many applications across audio, video, vision, and other computationally-intensive use cases."
A range of development tools and software products are already available or in development for the I6400 cores. The forthcoming L release of Android includes support for 64-bit MIPS. Hypervisors in development for the I-class cores will enable customers to take full advantage of hardware virtualization and enhanced multi-context security capabilities.
One of the first projects completed through the prpl open-source foundation is support for the MIPS64 r6 architecture in the QEMU open-source emulator, currently available here. With QEMU, developers can get started on developing applications and software for the 64-bit I6400.
Imagination is already engaged with multiple lead I6400 licensing partners. General availability is scheduled for December.
— Nick Flaherty writes about the semiconductor industry for EE Times and EE Times Europe.