BRISTOL, UK — Imagination Technologies has launched its I-class I6400 MIPS 64-bit processor with a focus on multithreading, multicore, and multicluster coherent processing that scales from a single core to hundreds.
The core is aimed at a wide range of applications, from embedded, mobile, digital consumer, and advanced communications to heavy lifting networking and storage. Imagination already has licensees in these areas, and the idea of clustering has driven key architectural choices between cores and between clusters. A new fabric to link cores into clusters gives significant advantages in being able to shut down individual cores to save power while maintaining coherency.
"Anyone can put multiple cores down on silicon today. Our cores were designed with coherency included to connect the cores together and all operate under a common environment, and you can also do it with multiple operating systems," Mark Throndson, director of processor marketing and business development at Imagination, told us.
A cluster is just one group of multicores. At the base level, if you buy the I6400 product, it can come in a quadcore configuration, all connected, and that would be one cluster of cores. This design was intended to take one cluster and scale it up to 64 clusters, each with six cores, using another level of technology, a fabric to connect these up together. We are not going into a lot of details on this fabric, but it's not part of the coherency manager. That ties six cores into a single cluster, and that could be connected into a larger multicluster solution.
All this aims at the larger networking and storage applications for customers such as Broadcom and Cavium. "We have companies taking MIPS cores north of 100 cores already, and we have designed for future extendibility, and I can certainly see between 100 and 200 cores," he said.
We have moved to a directory-based scheme. Rather than snooping in each of the cores, the manager maintains a directory that allows the cores to remain autonomous and be touched only when interventions are necessary to maintain coherency. This means you can run each core at its own frequency and voltage with full flexibility on each individual core. That is part of what makes it possible to scale to multiple clusters. It is sharing the directories across clusters. We have moved to an inclusive L2 cache that must include all the content of the L1 cache, so it isn't as much overhead.
A key element in the battle with ARM is the hardware multithreading option of up to four hardware threads per core. The I6400's simultaneous multithreading (SMT) technology makes it possible to execute multiple instructions from multiple threads every clock cycle.
"Our biggest competitor doesn't do multithreading at all," Throndson said. "We don't have MT in all our products. We tend to use it primarily in our mid-range products, which are about efficiency. That's why we are making a case for it here."
The other reason is using MT for mobile or DTV or STB or even the home networking market, where MIPS has a big footprint. "We believe MT should be more ubiquitous going forward, as it looks identical to multicore and provides a very simple scaling capability. You don't need different technology to take advantage of it."
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