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Intel Opens Door on 7nm, Foundry

EUV not needed at 10, 7nm
9/11/2014 07:45 AM EDT
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chipmonk0
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Re: 2.5D Breakthrough!
chipmonk0   9/14/2014 8:32:53 PM
"now all we need are chips routed to one edge "

and therein lies the rub.

Even if Memory suppliers agreed to re-design their die layout, redistribution like that would increase interconnect length, hence RC delays, when one of the key reasons for going to 2.5 d modules is breaking the Memory Wall ( interconnect related limits on Bandwidth, Sp. power for data transfer ).

This is of course assuming that the mechanical issues ( warpage during assembly, fatigue during service ) related to embedding Si Bridge chips in cheaper organic substrates with much higher CTE won't remain a factor.

And finally for a 5 die module the savings in Interposer area with the Bridge chip would be about 50 %. The additional cost of embed etc. will need to be lower than those savings.

_hm
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Operating voltage?
_hm   9/14/2014 12:53:35 PM
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At 7nm, what will be operating voltage? And current level will be very high for 4b transistors operating at 4GHz.

resistion
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Re: Moore's Law lives...at what cost!
resistion   9/13/2014 7:54:30 PM
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It's very layout-dependent.

goafrit
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Re: Moore's Law lives...at what cost!
goafrit   9/13/2014 9:51:31 AM
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>> They say they can keep making the chips at lower cost/transistor per node...but what's the premium foundry customers must pay?

Kudos to Intel for its continuous quest to extend the Moore's law. 7nm could be challenging and many not make lots of business sense except for Intel. I have come to believe that value will come from making smart chips and not higher speed and small size. But Intel is fixated on this down-scaling of feature sizes of transistors. I hope the cost can attract customers to it.

AZskibum
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Re: Moore's Law lives...at what cost!
AZskibum   9/12/2014 7:06:55 PM
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I would like to hear more about how they are reducing mask count on some layers rather than increasing it as they go from 14 nm to 7 nm. That is very counter-intuitive.

JimMcGregor
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Re: Moore's Law lives...at what cost!
JimMcGregor   9/12/2014 5:23:13 PM
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Having the technology is good, but what most people miss is that Intel typically locks down its process and tries to run everything on it. That is fine for your own products, but foundries need to be able to tweek the process to the customer's products. To be a major foundry player, Intel will have to break the "no process modification" mindset and having dedicated fabs may be the first step. But as Rick pointed out, even with the right foundry mindset, the cost of the technology may ultimately be the limiting factor.

Bruzzer
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Intel 14 nm design production cost
Bruzzer   9/12/2014 1:04:49 PM
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3 variant's Core M 14 nm design production cost on a good Haswell 22 nm fabrication day follows, so 14 nm Core M could be pricier, currently:

At 2% of production run $281.
At 6% of run $70.25
At 61% of run $28.10
At 100% of run $29.46

Likely design production cost of 14 nm Core M variants this early in run near $70.25, where $281 1K price is 4X $70.25 average marginal cost, on this Intel strategy cost : price check: 4x AMC.  

Compared to Haswell i3 dual mobile SIP three Core M variants best average marginal cost aim is $40 improving to $35; $0.42 down to $0.33 per mm^2 silicon area including 2.5D package.  Calculated at silicon area only / average marginal cost range $40 improving too $35.  

At full run learning curve, objective is same marginal cost as Haswell i3 dual mobile SIP at 181mm^2 dice area; $40 to $35.

14 nm Core M around $70.25 average marginal cost, currently, 83 mm^2 of silicon on embedded multi die interconnect suggests 4x area cost as Haswell dual mobile best; Core M $0.84 per mm^2 of silicon including interconnect calculated 83 mm^2 / $70.25 or $0.84 vs Haswell i3 dual moble SIP best at $0.21 per mm^2. 

Intel's production aim is two fold, to halve Core M production cost from $0.84 to $0.42 for same package area, and then attempt too perform that feat again, all the way down to 22 nm i3 dual mobile best at $0.21, which is likely not obtainable but $0.33 probably is.

Mike Bruzzone, Camp Marketing

msporer
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2.5D Breakthrough!
msporer   9/12/2014 12:30:24 PM
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Wow! No one commented yet on the 2.5D announcement.  This to me is the most significant development of all.   Interposer interconnect WITHOUT TSVs!  Silicon area a fraction of current interposer solutions.  No ultra-thin handling requirements.  Available next year.  Brilliant!  Now all we need are chips with the IO routed to the edge...

Susan Rambo
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Re: Intel foundry at dedicated facilities!
Susan Rambo   9/12/2014 12:43:38 AM
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@m00nshine, the Intel Developer Forum is on right now in San Francisco. That's why Intel is in the news.  You're also seeing a lot of Apple in the news this week.

m00nshine
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Re: Intel foundry at dedicated facilities!
m00nshine   9/11/2014 11:17:41 PM
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US laws prevent (last time I checked) the export of leading edge technology to China, which is why Fab68 at least started up only making chipsets on 65nm when intel was making processors on 32nm. That would suggest 10/7nm foundry in China is a long way off. Also, EE Times seems even more Intel centric than usual lately. Feels like I'm reading PR news releases from them here every other day or so.

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