Dubbed "SuperSpeed," USB 3.0 is increasingly being adopted in the electronics industry for applications requiring its high-bandwidth transfer capabilities of up to 5 Gbit/s. In many cases, designers are using USB 3.0 in conjunction with an FPGA. For example, automotive systems designers may be using an FPGA as part of the vision processing pipeline, and they may decide to employ USB 3.0 to access the video stream. Alternatively, designers may employ an FPGA as a bridging device.
A traditional solution implements the logical USB functionality inside the FPGA, but requires an external USB PHY (physical interface) chip. In this case, more than 70 pins/signals may be required to link the FPGA to the USB PHY.
Now, Altera Design Services Network partner System Level Solutions (SLS) has developed an Embedded USB 3.0 Device Controller IP that removes the need for an external PHY. By taking advantage of the FPGA's integrated transceivers, this IP allows designers to implement a USB 3.0-compatible link using only four pins for inter-chip connectivity.
The result is to reduce the BOM, system cost, and board space requirements. Furthermore, bringing the inter-chip connectivity requirements down from >70 to only 4 pins reduces routing congestion on the board and leaves the FPGA's pins free to perform other tasks.
This new solution is perfect for vision processing, USB bridges, media ports, USB port expanders, and any case where chip-to-chip USB 3.0 connectivity is required. Click here to discover more information about the Embedded USB 3.0 Device Controller IP from SLS.
— Max Maxfield, Editor of All Things Fun & Interesting