TORONTO -- The odds of Hybrid Memory Cube becoming a viable successor to conventional DRAM are improving with the release of specification 2.0 from the Hybrid Memory Cube Consortium (HMCC). Highlights of the HMCC 2.0 specification include increased data-rate speeds, from 15 Gbit/s in 1.0, up to 30 Gbit/s, and migrating the associated channel model from short reach (SR) to very short reach (VSR) to align with existing industry nomenclature. HMC uses a vertical conduit called through-silicon via (TSV) that electrically connects a stack of individual chips to combine high-performance logic with DRAM die. The memory modules are structured like a cube, instead of being placed flat on a motherboard, allowing dramatic performance improvements over DDR4 with lower power consumption.
Mike Black, technology strategist at HMCC co-founder Micron, says an early draft of the specification was provided to early adopters earlier this year so they could give feedback during the past six months. HMCC 2.0 has been in development for a year and a half. The HMCC is already looking ahead to next revision. “HMCC 3.0 is already a conversation.” For the immediate future the focus is on getting feedback on the latest specification and incorporating any changes that might further improve it.
When work began on the first specification, which was finalized and released in May 2013, 15 Gbit/s seemed like a good starting point, says Black, as it was at the top end of serial interfaces. The consortium has leveraged the work of other standards organizations to develop HMCC since its inception. It released an update to HMCC 1.0 in February.
The consortium itself was founded in October 2011 by co-developers Altera, Micron, Open-Silicon, Samsung Electronics, and Xilinx. Since then, the HMCC has grown to include more than 150 OEMs, enablers, and integrators who regularly participate in the development and discussion of HMC standards. Black expects HMC will find the most adoption in the high-performance computing segment during its early days and stay there for several years. Networking gear will be another area where it will find initial uptake.
Jim Handy, principal analyst with Objective Analysis, says the progress of the specification and growing participation in the consortium by various vendors indicate that HMC has the potential for widespread adoption and a future as the eventual replacement for DRAM. “It seems like we’re seeing some acceptance. Revision two shows there’s growing support for the standard. People are really taking a hard look at it.”
Putting on his Micron hat, Black said the company is developing commercial activities around HMC and preparing customers for the interface. It is already sampling HMC 1.0 SR devices, and expects to start shipping in mid-2015.
Handy notes that Intel has embraced HMC with its next-generation Intel Xeon Phi processor. Intel is collaborating with Micron to offer up to 16GB of high-performance memory and more than five times the sustained memory bandwidth compared with DDR4, along with improved power-efficiency and space-savings.
Like him, Handy sees HPC applications as an early user of HMC. “Supercomputing is usually the proving ground for concepts that later become commercial.” In addition, he sees high-end routers and networking gear using ASICs as a driving force for the adoption of HMC.
Coinciding with the release of HMCC 2.0 was consortium member Open-Silicon’s announcement of what the company said is the first HMC 2.0 controller as licensable intellectual property. Manohar Ayyagiri, Open-Silicon’s director of IP, says the controller will allow SoC designers to leverage the performance specifications of HMC 2.0 and builds on the experience the company already has working with earlier generations of HMC. He said Open-Silicon is already working with customers to integrate the HMC 2.0 controller IP into devices for applications such as high-speed networking equipment.
Open-Silicon’s HMC 2.0 memory controller IP is a soft macro implementation that is compliant with both HMC 1.0 and HMC 2.0, supporting the defined data rates of both standards. He says the memory controller IP is aimed at ASICs that support the growing bandwidth requirements of 100G and 400G networks.
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