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FeFET to Extend Moore's Law

1/15/2015 11:00 AM EST
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AKH0
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Re: One wonders ...
AKH0   1/16/2015 2:14:18 PM
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"First, not sure how this extends the ITRS roadmap". 

This is a great research topic, but let's not use the phrase "extend Moore's law" when refering to new technologies unless they really lead to smaller cost per transistor. No matter what material you use for the transistor and what physics is behind the operation of that transistor, it still needs 3 terminals. Unless your magic material or operation principle makes the dimensions smaller or makes the fabrication cost smaller, it does not fulfill Moore's law's requirement.

For example, one can refer to self-aligned double patterning (SADP), directional self-assembly, or self-aligned contacts and via as tricks that may extend Moore's law. But SiGe channel (at 28nm) or FinFET at 22/14 nm cannot be refered as technologies that extended Moore's law.

Extending this to the futuristic technologies, carbon nanotube, graphene, metal sulfides, III-V, Ge, tunnel FET and the like do not extend Moore's law. Vertical transistors, monolithic 3D, etc might.

ITRS is a constantly changing guideline that I am not sure has any practical use. For one, it is often more aggressive than what the current pace of the technology is. That's why it calls for a bunch of futuristics materials/structures well before you ever need them.

  

 

 

 

R_Colin_Johnson
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Re: Shipping simulations in volume
R_Colin_Johnson   1/16/2015 1:16:22 PM
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Thank you for your thoughtful comments. It is true that 99% of the new technologies invented never reach commercialism. And each scientist is pitching his as the most promising. When I interview them they admit that their are engineering hurtles to overcome, in this case forming a germanium channel. It can't be done "channel last" by implantation without destroying the barium titanate gate above with high temperatures, and it can't be done "channel first" because there is no good etch for barium titanate at the moment. This is the same problem that high-K dielectrics faced and solved. These researchers think they have a solution too. When I asked them what it was, he said "I could tell you, but then I'd have to kill you." So please accept my apology for not being able to guarantee that this approach will work. It is a work in progress, and I personally believe that these scientists are genuinely committed to solving the engineering problems facing them, but as I said 99% of new semiconductor designs fail to reach commercialization. The point of this article is to point out that barium titanate can be oriented vertically to make FeFETs, however there are engineering hurdles yet to clear for comercialization. I can only present what the scientists are doing and the engineering hurdles they face. And again thank you for giving me the opportunity to explain with your thoughtful comments.

acervinlawry
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Re: One wonders ...
acervinlawry   1/16/2015 12:58:42 PM
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One point about using ferroelectrics such as BaTiO3 is their dielectric constant is very high so the thickness of the gate dielectric canl also be much higher giving better reliability and lower gate leakage.

resistion
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Check out actual Vth data
resistion   1/16/2015 9:37:26 AM
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For one state, these transistors are on even at 0V!

GroovyGeek
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Re: Shipping simulations in volume
GroovyGeek   1/16/2015 5:11:03 AM
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Blah blah blah. EET editors should have an article template that they just forward to the Pis of this type of work Dear PI, please fill in the blanks below ___FET will revolutionize the electronics industry by extending Moore's Law by___ years/generations (please circle one). This will be achieved by growing___ on____ in layer by layer fashion (ed.note: be sure to only use materials nobody knows how to grow or we will not publish). The effect is only observable at___K (hint: if >77 this article will not be published). Anyone remember BisFETs that were going to achieve similar feats of nature and technology?

GeniusEE
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Shipping simulations in volume
GeniusEE   1/15/2015 9:34:53 PM
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So now we're going to go back to hermetic packaging of chips?

R_Colin_Johnson
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Re: One wonders ...
R_Colin_Johnson   1/15/2015 5:35:26 PM
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>I also wonder if the researchers had considered the Curie temperature of barium titanate.  At 120C, it is much too low to be useful in a CPU or memory

Thanks for the careful reading. The scientists are using other ferroelectric materials that tolerate higher temps, but barium titanate was convenient to prove the concept. Thanks again for the comment.

R_Colin_Johnson
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Re: One wonders ...
R_Colin_Johnson   1/15/2015 5:32:08 PM
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Some Guy, thanks for the excellent questions. Of course, as you mentioned, a lot of your questions will not be answered until that have some working FeFETs, but I'll take a stab.

1. "First, not sure how this extends the ITRS roadmap" Scientists claim that their material is faster and scales better.

2. " isn't Ge pretty leaky" Scientists say it depends on architecture and they are working to mitigate.

3. "are you going to have widely unpredictable inrush possibilities at power-on" Scientists say no, but will deal with issue when they have working circuits.

4. "investing a bunch of money on the faith of computer simulations alone". Scientists used computer simulation first, then verified its results in lab. The only thing they did not do yet was etch a Ge channel (they also plan to try GaAs for channel, but not in their lab.)

Thanks again for the comments.

gmorita
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Re: One wonders ...
gmorita   1/15/2015 2:51:22 PM
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I also wonder if the researchers had considered the Curie temperature of barium titanate.  At 120C, it is much too low to be useful in a CPU or memory.  I know there are other ferroelectric materials like PZT which has a Tc as high as 320C but I don't know how compatible it is with semiconductor precessing.

Some Guy
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One wonders ...
Some Guy   1/15/2015 12:26:50 PM
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First, not sure how this extends the ITRS roadmap, as the limitations have to do with not being able to go below one layer of atoms at the sub 5-nm scale. It won't mater if they are HfO2 or BaTiO3, you can't go thinner than a single layer of atoms (if one atom goes walkabout, the gate is toast, so for reliability reasons, maybe not even less than 2 layers of atoms). Just don't see how this gate addresses any of this.

Second, isn't Ge pretty leaky? What kind of power overhead is there going to be, and will it make the leakage at the 90-nm node look like a pitance?

Third, if all the gates are in their last state, what is the inrush going to look like? And are you going to have widely unpredictable inrush possibilities at power-on?

 

Finally, I'd sure want to build at least one of these gates for real to start getting an idea of what the real-world problems are going to be. The proof of the pudding is in the tasting, and investing a bunch of money on the faith of computer simulations alone is a great way to turn a big pile of cash into a little one.

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