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Marvell Shakes Up SoCs, DRAMs

CEO-led initiatives unveiled at ISSCC
2/23/2015 05:47 PM EST
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jhinkle0
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Re: AMD tried this in 2007
jhinkle0   3/13/2015 3:35:41 PM
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We had a moderate sized DRAM cache (sized as ratio cache to main memory) down on board for server systems we developed with the MXT (inline main memory compression) at IBM many years ago.  I believe it was 32MB vs up to 4GB main memory for our 1U 330 server.  Workloads and processing behavior have changed significantly since then, but for MXT the cache proved to effectively hide any major performance issues caused by compressing main memory.  Interesting point for that.. it was DDR when main memory was SDRAM, so it was faster than main capacity as well.

 

 

http://mxt.sourceforge.net/publications/mxtperformance.pdf

http://www.hotchips.org/wp-content/uploads/hc_archives/hc12/hc12pres_pdf/IBM-MXTpt1.PDF

JLWood
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An obvious question
JLWood   3/9/2015 2:09:41 PM
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DRAM can be written to infinitely.  Flash not so much.  I doubt many customers are going to get excited about systems with a built-in expiration date.

TommyV
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How about ECC?
TommyV   2/27/2015 11:48:30 AM
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I just hope they do not forget ECC protection on FLC.

Todays HDDs typically have 512Mb DDR2 DRAM for caching on them, SSDs use DRAM for the mapping data, but unfortunately nobody seems to have ECC here.

DRAMs tend to have bit-flips. We can see them when our PC or other electronics crash or behave erraticly. Servers use ECC and run stable for years. In fact the error correction is performed by the CPU on a 72 bit (64 data + 8 parity bits) wide memory bus.

On all drives you sometimes find a corrupted file, which might have been caused by a bit-flip of the DRAM during a Write. Or sometimes even the whole directory or block-map gets corrupted.

Drives do not have a 72 bit wide memory bus, but just use a single 16 bit wide DRAM chip on them. But with 'on chip ECC' DRAM (available from www.intelligentmemory.com/ECC-DRAM/) it would be possible to fill this gap.

 

andyzg
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Re: Paging reinvented?
andyzg   2/25/2015 3:59:34 AM
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I would expect that - given the relatively low latency of the SSD compared to an HDD - the paging is done in hardware, without involving the OS and its overhead.

nvqanh
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Re: DRAM maker reacts
nvqanh   2/24/2015 11:51:24 PM
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--> @Rick, I'm familiar with DRAM and Flash memory power consumption, but I think that if missing rate is small then (1GB DRAM + 4GB Flash) may require less energy than 4GB DRAM. Let me show my this humble opinion in a quantitative way.
     Assume:
      Energy consumed by one access to 4GB DRAM = 1.2 (D) x Energy consumed by one access to 1GB SRAM (E)
      Energy consumed by one access to 4GB Flash (at miss) = 10  (F) x Energy consumed by one access to 4GB DRAM
      (though Flash is considered lower power then DRAM, I assume 10x in consideration of the fact that access to Flash is done in Page-unit not in byte-unit like the case of DRAM)
     Now, let say miss rate is 0.05% (M) (Antutu benchmark), then for N access times
      FLC approach burns:       N * E + (10 * 1,2*E) * N * 0.05 = 1,06 * N * E
      Conventional burns:       N * 1,2 * E                     = 1,20 * N * E
     I turns out that FLC approach is better. In general if (1+ F*D*M) < D, then FLC is better. So it would be helpful if you can give some real data related to D and F.
     You may say that I missed to count the fact that during miss time, the total system has to be stalled and still power is consumed,
     but this depends on system level and I've not taken into account leakage, DRAM refresh power consumption which I think is worse in case of 4GB DRAM approach.
     
    Furthermore, according to this quote "Sutardja said FLC could cut the main memory needed in a system by as much as a factor of ten, promising lower cost, lighter and higher performance products", power consumption is not mentioned as and an advantage of this approach, but cost and performance. So we may discuss more about these factors.

rick merritt
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AMD tried this in 2007
rick merritt   2/24/2015 10:13:49 PM
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Another engineer told me AMD considered an external DRAM cache between the CPU and main mempry in 2007 and decided it wasn't worth the effort.

sranje
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NAND memory
sranje   2/24/2015 6:28:25 PM
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A question for our Mobile NAND module (NAND + controller) experts:

 In iPhone-6 NAND module has conformal EMI shielding. Is it beceause components are getting close together, there are a lot of radios and antennas, NAND lithography is finer and NAND needs protection from RFI and EMI interferences?

Am I correct? Marvell is an early player in WE and IoT -- will conformal EMI shielding spread to WE and IoT?

Many thanks in advance  

Wilco1
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Paging reinvented?
Wilco1   2/24/2015 4:34:03 PM
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Modern SSDs support 100K random 4KB read ops/s, so the performance difference with DRAM is only about 30 times for bandwidth and 60 times for latency. So the idea will work fine - in fact the low latency and high bandwidth means SSDs are much better at demand paging than HDs even with a much smaller DRAM size.

However what I don't get is how does this improve on traditional paging by the OS? Also how do they use much larger pages than the OS uses? A 32KB physical page may contain only 1 4KB page that is in use by the OS...

HankWalker
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Re: DRAM maker reacts
HankWalker   2/24/2015 2:41:36 PM
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The answer is that it depends. Flash is 1000x slower than DRAM, but 10x cheaper. If your working set will fit into the small DRAM and it is mostly-read, then fine, but if the working set is larger than the small DRAM, performance will be terrible. And obviously you can't have large numbers of writes hitting the flash.

So each system would have to be evaluated based on its application software. It would not be appropriate to just throw it in as another caching layer.

 

rick merritt
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DRAM maker reacts
rick merritt   2/24/2015 10:55:32 AM
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One DRAM guru I saw at ISSCC said the FLC concept does not make sense. Transfering more data more quickly between a small DRAM cache and flash storage would burn up more energy, not less, than today's approaches.

 

 

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