TORONTO – Spansion is following in the footsteps of its HyperBus interface and HyperFlash announcements last year with the introduction of a companion RAM device: HyperRAM is designed for use in SoCs and microcontrollers (MCUs) where both RAM and flash are connected to the same Hyperbus Interface.
Jackson Huang, Spansion's VP of product marketing and ecosystem, said the company will begin sampling 64Mb HyperRAM in the second quarter of this year. HyperRAM communicates at the same speed as HyperFlash, with a read throughput of up to 333 MB/s and 36ns array read/write latency. Putting them together on HyperBus lowers the pin count from around 40 to 12, he said.
The reduced pin count means a smaller package of 21x21 BGA compared to 23x23 is possible, said Huang, although the reduction may vary depending on the specific SoC as use cases require. For instance, some SoC makers might choose to use the saved pins for additional functions and features. A smaller package also translates into cost savings, he said, as the overall size of the board can be reduced.
Huang said the other appeal is a simpler design. “Board designers only have to worry about HyperBus pins that talk to both HyperFlash and the HyperRAM.” The HyperBus interface consists of an 8-pin address/data bus, a differential clock and one chip select and a read data strobe for the controller.
Like its HyperFlash does, Spansion’s HyperRAM connects to the company’s proprietary 12-pin HyperBus Interface
Spansion sees HyperRAM as an alternative to the commonly used options of SRAM or PSRAM using a parallel bus with more pins, he said. The company was able to leverage more than four years of development on its HyperBus and HyperFlash technologies and apply it to the development of HyperRAM, said Huang. Architectural changes were made, with addressing and data running in parallel to facilitate faster communication with the RAM. The challenge in the design process was to avoid conflicts. “We had to make sure both signals were compatible at the system level.”
Spansion expects demand for faster speeds and faster devices, said Huang, and will look to add features when combining HyperRAM and HyperFlash together based on customer requests. However, he said, they don’t have to use both. For example, if there is around 300MBps of read and write throughput, using HyperRAM and HyperFlash together makes a lot of sense, but DDR3 with HyperFlash might be better for more high intensity computational usage, said Huang.
Applications that could take advantage of HyperRAM’s faster read time and combining it with HyperFlash include automotive, said Huang, such as instrument clusters, infotainment and advanced driver assistance systems, as well as industrial and factory automation, medical equipment, and Internet of Things (IoT) devices.
Tom Hackenberg, principal analyst for MCUs and DSPs at IHS Global, said that as with anything new, the proof will be in the field performance of HyperRAM. However, given what Spansion has designed, it is fairly unique due its use of the HyperBus, he said, as it reduces the pin count and simplifies the movement of data back and forth. (Most systems have a controller, non-volatile memory and RAM with a typical bus that is more than 40 pins.) Right now, Hackenberg doesn’t see an equivalent technology on the market.
Hackenberg said HyperRAM addresses a trend toward the simplicity designers of embedded systems are looking for. “There’s a lot of demand for a little more performance without adding a lot more complexity or cost.” That will make it useful for IoT, industrial and automotive applications, where the goal is to design and get to market quickly without needing something complex with more bells and whistles.
One application in automotive that Hackenberg said would benefit is advanced driver systems with rear view cameras that must come online quickly, sometimes right after a driver starts the car and wants to back out of a parking spot. Infotainment systems in vehicles are becoming more demanding with increased use of 3D graphics in the cockpit, he said.
Hackenberg said Spansion is touting speeds comparable to that of DDR2 and DDR3, so while HyperRAM is unlikely to unseat DDR4, for deeply embedded systems that need some “extra oomph,” HyperRAM looks promising.
Jim Handy, principal analyst with Objective Analysis, said designers using MCUs are always looking to reduce the pin count, and DRAM has a pretty high pin count. Being able to reduce the package size could also keep costs down. “There will be savings. It’s just a question as to how significant they are.”
Handy also sees potential for HyperRAM in the automotive space, where Spansion already plays, noting the design meets the extreme temperature ranges for −40°C to 105°C for devices in vehicles. He said Spansion would likely find itself competing with applications that use SPI flash, and that HyperRAM would make sense in areas where it could replace DRAM.