SAN JOSE, Calif. — More than 100 chips in or headed for production have taped out using FinFET-based process technologies, according to EDA tool vendor Synopsys Inc. The chips include a quad ARM Cortex-A72 device made in TSMC’s 16nm process, it said.
Synopsys claims its Galaxy Design Platform has been used by 90 percent of the production-bound FinFET chips that have taped out to date. The news was released the same day archrival Cadence Design Systems announced Innovus, its next-generation physical design tool which claims significant speed ups in FinFET and planar processes.
The news suggests TSMC and Samsung are running neck-and-neck to close the gap with Intel which has been in production with 14nm processors for several months.
In the past month, HiSilicon Technologies, the silicon division of China telecom giant Huawei, taped out at TSMC a 16nm quad A72 device with more than 50 million instances. It has a 16nm A57 device also made in the fab and already shipping in systems, said Mary Ann White, director of product marketing for Synopsys’ Galaxy Design Platform.
Achronix, Global Unichip Corp., Marvell, Netronome, Nvidia and Samsung also have taped out production chips in FinFET processes at TSMC, Globalfoundries, Intel or Samsung fabs, Synopsys said. The chips target markets ranging from consumer electronics to wireless, graphics, microprocessors and networking devices.
Samsung announced at Mobile World Congress its first 14nm FinFET chip, an Exynos applications processor, will power its new Galaxy S6 smartphones. Earlier this year sources said Samsung was ahead of TSMC in FinFET production, but the latest news indicates the two are still in a dead heat.
“Two or three years ago Intel was ahead [in process technology] and foundries were striving to catch up, [but now]…perhaps some of that gap is closing,” said Saleem Haider, a senior marketing director at Synopsys. “For FinFET processes, we are very much in the phase where customers are calling on us for support with production designs,” he said.
Most of the issues around the need for double-patterning lithography got worked out in the 20nm nodes with chip designs that started as early as 2005, said White. At the 10nm node, foundries are starting to choose diverging paths with some adopting self-aligned double patterning and others moving to triple patterning, she said.
“Our goal is to provide encapsulation the shields designers from these effects as much as possible,” said Haider, noting they still face challenges with large, complex files that require relatively long turn processing times.
EDA analyst Gary Smith said Synopsys has ahead in physical design tools, but Cadence is working to catch up. Cadence claims its new Innovus Implementation System “provides typically 10 to 20 percent better power-performance-area and up to 10x full-flow speedup and capacity gain at advanced 16/14/10nm FinFET processes and established process nodes.”
Cadence enabled multi-threading throughout the software. The program also enables complex designs with more than 10 million instances, it said.
“We partnered closely with Cadence to use the Innovus Implementation System during the development of our ARM Cortex-A72 processor,” said Noel Hurley, general manager of ARM’s CPU group, speaking in a Cadence press release. “This demonstrated a 5x runtime improvement over previous projects and will deliver more than 2.6GHz performance within our area target,” he added.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times