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Cypress Expands Error Correcting Code For SRAM

4/24/2015 06:00 PM EDT
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Re: There is also on-chip ECC for DRAMs
TommyV   4/29/2015 10:56:34 AM
HEDE0 wrote: "Nice to detect soft errors inside the memory device itself. Hard errors on the interface to the memory are not detected nor corrected if ECC is located in the memory device. For many applications this would be insufficient."

Well, I tend to disagree for two reasons:

1) We are talking about applications that per today have no ECC protection at all! For example automotive electronics, medical devices, industrial applications, networking devices, control-boards, etc etc. A bit flip causes random malfunction or data corruption. Even harddisks and SSD drives use a DRAM for write-buffering/caching. A bit flip can cause those annoying messages "file can not be opened, it is corrupted".

Real life examples (not safety critical, but annoying): From our PC and Smartphones we know bit flips in the way that the mouse-pointer sometimes freezes, menus do not open any more, programs hang, etc. Our settop boxes, PVR, TV sets, wifi-routers and many other electronics sometimes behave strangely or crash... we all know how to reset these devices. Why did we have to learn that? Simple because electronics sometimes have a problem. And many or most of these issues are caused by a bit-flip. Now look at a Server having ECC. Interesting enough, it works for years without failing.

What is better? Having ECC inside the SRAM/DRAM resulting in an exponentially higher availability and reliability or having no ECC at all?


2) But now coming to your point of the interface.

Memory components are the most vulnerable devices as they are holding their data "charge-based". A memory chip with 1 Gigabit capacity has 1 billion little memory cells on a chip of 10x10mm in size. Can you imagine how little each memory-cell is and how much charge is deciding about each databit being 0 or 1 ? This charge is extremely small and very very sensitive to disturbances. On DRAM, it requires periodic refreshing every few milliseconds to make sure the data is kept.

The lines from the memory to the controller are wires that are a hundred-thousand times larger than the memory-cells. This wire is not expected to "hold a charge", but just to let the charge pass through. It is close to impossible that a bit gets lots "on the way".

But, if the timing-settings between controller and memory are not correctly programmed or if the board-layout has a problem (i.e. length mismatches, wrong termination, etc), then you will also get errors. These types of errors will not be ECC-correctable "bit-flips", but typically be massive fails where ECC won't help much.

ECC is protecting only from single bit errors. Up to one bit-flip per each 64 bits can be corrected. If the board-layout is correctly done and the interface is well programmed, then you won't need to fear errors on the transmission-way between the memory and the CPU/controller-chip. Those errors wouldn't be ECC correctable anyway.

But ECC protects very very well from the fairly common single-bit-errors that happen in each and every memory chip from time to time. ECC is the reason why servers are working reliable and stable for years. For a long time, ECC was limited to be used in servers, because ECC was a CPU-functionality.

Now with the new SRAM and DRAMs having "on chip ECC", every application you can dream of can be made super-reliable, even heat and radiation-proof (because heat and radiation also mainly cause single bit errors in memory-chips)!




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Re: There is also on-chip ECC for DRAMs
HEDE0   4/29/2015 5:16:10 AM
Nice to detect soft errors inside the memory device itself. Hard errors on the interface to the memory are not detected nor corrected if ECC is located in the memory device. For many applications this would be insufficient.

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There is also on-chip ECC for DRAMs
TommyV   4/28/2015 8:19:17 AM
Having on-chip ECC is the way to go for all memory, not only for SRAM, but even more for DRAM.

While SRAM is a niche-memory today, DRAM is used in almost every application.
And DRAM is even more sensitive to disturbances of any kind than SRAMs. Bit-flips can corrupt data or hang up the software which is exectuted from the RAM.

To perform an ECC error correction on DRAM, an ECC-capable CPU with a 72 bit memory-databus was required in the past. This limited the use to high end servers before.

Now Intelligent Memory released DRAMs with integrated "on-chip" ECC error correction named ECC DRAM ( The technology is very similar to the way Cypress integrates ECC into their SRAMs. With on-chip ECC the memory-components verify and correct their data on their own before it is transferred to the CPU. This makes it possible to use ECC SRAM and ECC DRAM on any existing application without redesigning. Every application that is required to be reliable and stable could benefit from memory with integrated ECC error correction.



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