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New Spectra-Q Engine at Heart of Altera's Quartus II FPGA Environment

5/11/2015 05:00 PM EDT
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KarlS01
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Finally a sensible flow.
KarlS01   5/13/2015 9:40:09 AM
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Kevin Morris over at EE Journal expanded a little on the design flow and ikt sounds like the approach we used to develop a family of peripherals and a bus system(interconnect) to build micro-controller based products. 

It just did not makes sense to essentially re-design and re-package everything so we had pluggable hardware with "common adapter code" to provide a SW interface to the programmer and a command/response interface to the HW(driver).

As an aside:  management was excited because theoretically a controller could drive and receive the peripheral interface with only a driver/receiver.  It was very hard to explain that the controller could not meet the response times.

This is analogous because the system generates the interconnect and the IP provides the HW interface.

HDL synthesis inference types will be reluctant and "timung closure" will, only apply to IP blocks so that aspect will get some criticism.

At some point design must stop when timing is good enough so a product can ship.  This is a good approach -- now if we had a way to model HW and SW together to optimize function partitioning...........

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