PORTLAND, Ore.--The entire semiconductor industry is trying to find a way to exploit the higher electron mobility of indium, gallium and arsenide (InGaAs) without switching from silicon substrates, including the leaders at Intel and Samsung. IBM has demonstrated how to achieve this with standard CMOS processing.
Last month IBM showed a technique of putting III-V compounds of InGaAs onto silicon-on-oxide (SOI) wafers, but now a different research group claims to have found an even better way that uses regular bulk-silicon wafers and have fabricated the InGaAs-on-silicon FinFETs to prove it.
"Starting from a bulk silicon wafer, instead of SOI, we first put down an oxide layer and make a trench through to the silicon below, then grow the indium gallium arsenide from that seed--its a very manufacturable process," Jean Fompeyrine, manager of advanced functional materials told EE Times. Fompeyrine performed the work with Lukas Czornomaz, an advanced CMOS scientist with IBM Research.
The InGaAs grows upward from a seed with many defects (left) then continues horizontally across the wafer virtually defect free, after which the ends are etched off leaving a perfectly non-strained crystalline transistor channel (green) of III-V material atop a buried oxide (BOX) on a standard silicon substrate (no need for silicon on insulator--SOI) with a metal source, drain and gate (grey) using a high-k dielectric (red) all surrounded by an interlayer dielectric (yellow) of silicon dioxide.
Using a method similar to that of Belgium-based microelectronics research center Imec, IBM's process has a twist that makes all the difference. Imec's growth was vertical only, but IBM only begins vertically then coaxes the InGaAs to turn horizontal and inward. The process stops making the lattice mismatch defects it was making during the vertical column growth pattern, according to Fompeyrine.
"Our method uses confined epitaxial overgrowth--or CELO--which results in InGaAs epitaxial structures with very low defectivity, which fulfills the requirements of both ultra-thin-body and fin-based advanced CMOS nodes," Fompeyrine said.
Here IBM demonstrates that its confined epitaxial lateral overgrowth (CELO) technique even works with FinFETs on a standard silicon substrate.
The previous IBM researchers using SOI wafers had multi-gate metal-oxide-semiconductor (MOS) field-effect transistors (FETs), but they were not regular FinFETs, because there were too many defects from the lattice mismatch. However, the new CELO process has very few InGaAs defects, allowing IBM to build both planar and finned FETs using a III-V material as their high-speed channel (see photos) above buried oxide (BOX).
"Other approaches use aspect ratio trapping--like Imec--instead of growing on the wafer, but our CELO process goes one step further by just beginning growth in a trench, where there are many defects, then turning the growth 90 degrees when it comes out of the trench where the planar growth produces very few defects," Fompeyrine said.
The table demonstrates IBM's belief that it has finally solved all the outstanding problems (green) in depositing III-V transistor channels.
The CELO approach resulted in gate-first self-aligned FinFETs with excellent electrical characteristics which outperformed similar sized silicon transistors. The InGaAs FinFETs had 100nm long gates, 50nm wide fins, 250nm wide contacts and was 30nm thick. Since no processes other than standard CMOS were used, IBM claims the III-V on silicon CELO technology has "significant potential" for high-volume manufacturing at advanced CMOS nodes.
Get all the details in the paper titled "Confined Epitaxial Lateral Overgrowth (CELO): A Novel Concept for Scalable Integration of CMOS-compatible InGaAs-on-insulator MOSFETs on Large-Area Si Substrates" presented today at the 2015 Symposia on VLSI Technology and Circuits (June 16-18, Kyoto, Japan).
— R. Colin Johnson, Advanced Technology Editor, EE Times
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