SAN JOSE, Calif. — Engineers have 16 GTransfers/second up and running in the lab for PCI Express 4.0, aka Gen 4. The bad news is this is the last turn of the crank for a copper version of the interconnect and, despite progress, a final 1.0 version of the spec may not be ready until early 2017.
Developers in the PCI SIG hope to complete a 0.7 version of the spec by the end of the year, at which stage they expect no major changes to the technology. Getting out ahead of the standard, Cadence and Synopsys will both announce PCI Express 4.0 PHY and controller blocks at the annual PCI SIG conference here June 23.
The big work ahead for the standard is in fine tuning the link and getting engineers to agree on its parameters. The work is significant because the greater speed translates into shorter reach generating some new costs for retimers in some systems such as servers which make heavy use of PCIe.
The spec may be taking a bit longer to finish than previous PCIe generations. That’s understandable given the SIG chose to go for what they thought was the maximum possible data rate, squeezing copper links for all they could deliver, twice as much as in today’s Gen 3 products.
“We are getting 16G, something no one thought was possible a few years ago,” said Al Yanes, president of the PCI SIG in an interview with EE Times.
“The base distance is still being validated but it’s typically 7 inches or so,” said Yanes who has led the organization for several years. “Longer channels of 15 inches or so with two connectors will have retimers, but Gen 3 has used retimers -- now we will need to use them for shorter long channels,” he said.
Gen 4 will use a new connector but the spec will be backward compatible mechanically and electrically with today’s 8GT Gen 3.
“We’ve done a lot of analysis on the connector -- we tried everything possible,” said Yanes. “We have some top engineers in our electrical work group and they’ve come through -- its exciting to see the amount of activity and participation,” he said.
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In its last copper version, PCIe will double its base data rate.