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IBM Leapfrogs Intel to 7nm

EUV FinFETs Use Germanium Channel
7/9/2015 00:01 AM EDT
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R_Colin_Johnson
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Re: Cadence Innovus Implementation System has been qualified on Samsung Foundry’s latest 10-nanometer (10nm) process.
R_Colin_Johnson   2/21/2016 5:48:16 PM
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I love your predictions that the "7nm FinFET is the last FinFET device to be manufactured but will provide also the largest inversion currents." Your deep understanding of the processes and the approaching end of the International Technology Roadmap for Semiconductors will be of great value to all out readers. Thank you for taking the time to share you wealth of semiconductor knowledge. BTW what do you think lies beyond the end of the road?

michigan0
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Cadence Innovus Implementation System has been qualified on Samsung Foundry’s latest 10-nanometer (10nm) process.
michigan0   2/21/2016 5:02:33 PM
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Sang Kim


Cadence Design Systems recently announced that the Cadence 
Innovus Implementation System has been qualified on 
Samsung Foundry's latest 10-nanometer (10nm) process. With 
no 22nm and 14nm FinFET process and manufacturing 
learnings, Samsung, however, appears to have qualified 10nm 
FinFET process leapfrogging Intel and TSMC. Lets take a close 
look.

Intel's first 22nm FinFET in volume manufactured for a number 
of years has the flowing three distinct regions: 1) largest 
periphery region with finW(width) equal to 22nm at the bottom 
to finW=7nm at the top. 2) the smallest inversion region with 
finW equal to 7nm at the bottom to 4nm at the top and 3) a 
small dome shaped structure at the bottom equal to 4nm and 
upward is subject to quantum mechanical confinement effects 
or not subject to the classical device physics, thus it doesn't 
contribute to the device drive currents. Therefore, the largest 
drive currents or on-currents for 22nm FinFET are contributed 
by the periphery regions.

Intel's 14nm FinFET is volume manufactured for almost three 
years. Where does the Intel's 14nm drive currents or on-currents come from? They don't come all from the periphery 
regions because the periphery regions significantly decrease 
at 14nm FinFET while the inversion region increases. The 
increase in inversion region possibly more than compensate 
the decrease in the periphery region. 

Intel's 10nm FinFET will be manufactured possibly in 2016 or 
this year. The periphery region further decreases but the 
inversion region increases significantly compared with 14nm
FinFET resulting in larger inversion currents for 10nm FinFET.

The uniqueness of 7nm FinFET is that the periphery region 
no longer exists, Instead the entire 7nm FinFET channel is 
now inverted, showing the the largest inversion currents. 
The 7nm FinFET, however, is the end of FinFET technology 
because 5nm FinFET and below can't be manufactured 
because depositing such ultrathin 5nm filum uniformly and 
reliably over 12" wafers at the manufacturing line is 
extremely difficult or not manufacturable, thus the end 
of FinFET technology, also the end of ITRS(International 
Technology Roadmap for Semiconductors). Therefore, 7nm 
FinFET is the last FinFET device to be manufactured but 
will provide also the largest inversion currents.

R_Colin_Johnson
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Re: Uiqueness of 7nm FinFET
R_Colin_Johnson   2/11/2016 10:26:58 AM
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Thank you for your updated analysis of IBM's 7nm process. A lot has happened since it was published in July 2015. IBM was claiming that its 7nm process leapfrogged Intel in the research lab, not in production. Of course, since then Intel has released more details about its quest for 5nm, making IBM's claim almost irrelevant now in 2016. Nevertheless, thank you for your valuable insights--I and many of our readers, I'm guessing--learned a thing or two from you deep understanding of advanded nodes. Thanks again.

michigan0
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Uiqueness of 7nm FinFET
michigan0   2/10/2016 11:21:04 PM
Sang Kim


Intel's 22nm and 14nm FinFETs are volume manufactured for 
over 2 years or more and TSMC's 16nm FinFET will be 
manufactured possibly in 2016 or this year. The FinFET's drive 
currents predominantly come from the periphery regions for 
22nm, 14nm and 10nm FinFETs. 

The uniqueness of 7nm FinFET is that its drive currents don't 
come from peripheries any more because 7nm FinFET dose 
not have such periphery regions that 22nm, 14nm and 10nm 
FinFETs have but shows the largest drive current or on-current. Then where such largest drive current comes from? 
Along the peripheries? FinW(width) equal to 7nm at the bottom 
and 4nm at the top is so narrow that the entire 7nm FinFET 
area becomes fully inverted or volume inverted just like a 
double gate transistor resulting in large inversion or volume 
inversion currents.

The key issue with 7nm FinFET is how can suppress the leakage 
currents due to the short channel effects for such short channel 
7nm FinFET? According to FinFET device physics as long as 
finW(width) at the bottom of fin is equal to or smaller than gate 
length(Lg) or channel length, the leakage currents are 
suppressed. That is why 7nm FinFET is considered as the end of 
ITRS(International Roadmap for Semiconductors). This is 
because the 5nm FinFET and beyond can't be manufactured 
because depositing such ultrathin 5nm filum uniformly and 
reliably across 12" wafers at the manufacturing line is 
extremely difficult or not manufacturable. If not 
manufacturable, the end of the debate! That is why 7nm FinFET 
is the last node to be manufactured.





michigan0
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IBM Leapfrogs Intel to 7nm
michigan0   1/24/2016 5:44:06 PM
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Sang Kim


First, Intel's 22nm FinFETs and 14nm FinFETs are in mass 
production over 2 years and 10nm FinFETs are manufactured 
possibly in 2016 or this year. TSMC's 16nm FinFETs are 
manufactured possibly in 2016 or this year also but IBM and 
its Alliance members have not manufactured FinFET at any 
technology node yet but that doesn't rule out that IBM could 
leapfrogs Intel to 7nm as claimed although it appears to be 
now an impossible task for IBM to skip several FinFET tech 
nodes and with no prior process and manufacturing learnings. 
These are the big challenges for IBM's 7nm tech race. lets 
take a close look. 

The uniqueness with 7nm FinFET is that the overall finW
(width) equal to 7nm(bottom) to 4nm(top) is so narrow 
that inversion or volume inversion takes place as occurs in 
the double gate transistors resulting in large inversion or 
volume inversion currents. Therefore, the implementation 
of IBM's secret sauce or the silicon germanium channel is 
not only unnecessary even if manufacture-able but 
detrimental because inversion or volume inversion can't 
take place in the dopped channel such as silicon germanium 
channel.

In my opinion the right question should be, can IBM leapfrog 
Intel to 7nm? Instead of "IBM leapfrogs Intel to 7nm". The 
answerer to that question is already answered above, 
not likely!

resistion
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Re: Unavoidable defects (paper by IBM and Toppan)
resistion   8/13/2015 9:44:04 AM
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It's relatively hot off the press. They hadn't talked about this in a while, so it was a good update. It's not so node-specific, by the way. And of course, very limited audience announcement.

R_Colin_Johnson
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Re: Unavoidable defects (paper by IBM and Toppan)
R_Colin_Johnson   8/13/2015 9:35:31 AM
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Very interesting--I haven't seen that paper. I suppose at 7nm even atomic-sized defects could affect yields. There's still a long-way to go to perfect EUV.

resistion
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Unavoidable defects (paper by IBM and Toppan)
resistion   8/13/2015 9:06:25 AM
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ENDEAVOUR to Understand EUV Buried Defect Printability

Photomask Japan 2015: Photomask and Next-Generation Lithography Mask Technology XXII

Proc. of SPIE Vol. 9658, 96580G

NAP-PD (Native Acting Phase – Programmed Defects), otherwise known as buried program defects, with attributes very similar to native defects, are successfully fabricated using a high accuracy overlay technique. The defect detectability and visibility are analyzed with conventional phase contrast blank inspection @193 nm wavelength, pattern inspection @193 nm wavelength and SEM. The mask is also printed on wafer and printability is discussed. Finally, the inspection sensitivity and wafer printability are compared, leading to the observation that the current blank and pattern inspection sensitivity is not enough to detect all of the printable defects. © (2015) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

These defects are less than 1 nm tall (atomic height), yet can affect printing.

resistion
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Re: Increasing the Yield
resistion   8/13/2015 9:02:21 AM
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Yes the energy output needs to be much more than today. Then there is enough to expose the resist, as the mirror layers start to melt into each other.

resistion
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Re: Multiple passes
resistion   8/13/2015 9:00:59 AM
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Is it really 65 eV, the usual source is 13.5 nm or 92 eV. But you are right about the higher photon energy and its very easy absorption. More energy goes into the mirrors than exposing the resist (unlike ArF immersion).

I doubt EUV will smooth things out without a significantly higher dose than used for ArF, that's to keep the number of EUV photons in your scheme comparable to the number of ArF photons.

Interesting thoughts.

Despite IBM's appearance of championing EUV, I found a paper this year where they clearly showed mask defects that cannot be detected today, and probably unavoidable anyway. More on this below.

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