Intel is expected to announced extensions in SkyLake Xeon SoCs to the DDR4 bus to accommodate 3-D Crosspoint memories.
Eggleston believes 3-D Crosspoint is a “re-branded form of phase-change memory,” a variant of something Intel demonstrated in 2009. Another analysis recently concluded the Intel/Micron technology is definitely not PCM. Intel and Micron have not detailed the technology so far.
In general, crosspoint memories “are not ideal…I spent more than five years building them, and they have a cost problem associated with the lithography needed,” he said, noting a 20nm design would require 20 passes through a stepper for some critical layers.
Micron told investors earlier this year it will start producing two new memory technologies this year, the first a relatively high cost one coming this year, Eggleston noted. “I might expect some memory makers without Crosspoint will bring down their DRAM prices rapidly to try to squeeze out this technique,” he said.
Among its other hurdles, phase-change memories “consume a lot of energy, so I think they will have trouble meeting the 12W power window for a standard DIMM,” he said. “So this probably requires a new thermal design and that’s a major undertaking, hard for server makers,” he added.
The Intel/Micron Crosspoint “shows promise, but needs a lot of mainly software support and will face challenges hitting a price significantly below DRAM, so I am not expecting big changes anytime soon,” said Jim Handy, a principal analyst for Objective Analysis (Los Gatos, Calif.), in a related talk.
Besides extensions to the DDR bus, the chips will require support for persistent memory both in the operating system and in applications, Handy said. The Storage Networking Industry Association has done work in this area and Intel said it will have new CPU instruction to assist, Handy added.
Eggleston noted that Marvell’s Final Level Cache concept, announced in February, is similar to the Intel approach.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times