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Garcia-Lasheras
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Re: RISC-V viability
Garcia-Lasheras   9/1/2015 6:28:06 PM
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@pattrsn: "Clearly, the marketplace has room for more instruction sets than just ARMv7, so there is room for RISC-V"


As FPGA technology becomes more affordable, not only there is plenty of room , but a need for a truly free/open new ISA... even more if the one we are talking about has support for different bus width sizes: from simple control to DSP size in a single package!

pattrsn
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Re: RISC-V viability
pattrsn   9/1/2015 6:45:49 AM
I checked with ARM. AArch32 is an optional part of the ARMv8 architecture.

Thus, some ARMv8 cores will include it, some won't. I'm pretty sure the NVDIA ARMv8 core doesn't include AArch32, for example.

My original point was commenting on the the remark that the industry wants a single instruction set architecture. Even ARM offers basically three: ARMv7, Thumb-2, and ARMv8, depending on whether you think Thumb-2 is part of ARMv7 or not.

Even if you believe anytihng from ARM is a single instruction set, that is still ignoring the billions of cores shipped last year using Tensilica, ARC,  and MIPS instruction sets.

Clearly, the marketplace has room for more instruction sets than just ARMv7, so there is room for RISC-V

betajet
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Re: RISC-V viability
betajet   8/29/2015 12:47:03 PM
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While I haven't downloaded the ARMv8-A Architectural Reference Manual (ARM ARM), the summary page I link to above implies that AArch32 is required for ARMv8-A.  It's included in all the current ARMv8-A processors: Cortex-A72, Cortex-A57, and Cortex-A53.  So any devices based on those processors should be able to run 32-bit user-space applications.

I took a quick look at the ARMv8-R page.  According to the ARMv8-R Architectural Overview linked to on that page, ARMv8-R is a 32-bit architecture only implementing AArch32.

pattrsn
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Re: RISC-V viability
pattrsn   8/29/2015 9:34:23 AM
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I can't tell from documentation if Aarch32 is optional for V8 or required.

betajet
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Re: RISC-V viability
betajet   8/28/2015 12:13:50 PM
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pattrsn wrote: Note that ARMv7 and ARMv8 are completely different instrution set architectures (ISA), which are not binary compatible.

ARMv8 has two instruction sets, the 64-bit AArch64 and the 32-bit AArch32.  My understanding is that AArch32 can run existing user-space ARMv7 binaries for backward compatibility.  AArch32 includes Thumb-2 instructions (now called T32).

ARMv8-A Architecture

pattrsn
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RISC-V viability
pattrsn   8/28/2015 9:09:04 AM
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Note that ARMv7 and ARMv8 are completely different instrution set architectures (ISA), which are not binary compatible. If the market really demanded processors that run binary compatible ARMv7 core, there would be no market for ARMv8, which there obviously is. Thus, there is clearly room for more than one ISA, even from ARM.

Moreover, here is data for shipments in 2014:

12.0B ARM

  2.0B Tensilica

  1.5B ARC

  0.8B MIPS

Clearly, billions of chips were shipped last year using ISAs other than those from ARM.  

For applications with embedded software where the instrution set is invisible, such as IoT, seems to me that the market IS open to lots of ISAs. Why not a free and open one like RISC-V?

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