PORTLAND, Ore.—The Semiconductor Research Corporation (SRC) is already running the Nanoelectronics Research Initiative (NRI) and the Semiconductor Technology Advanced Research Network (STARnet), which are developing post-silicon next-generation technologies to be shared by IBM, Intel, Micron, and Texas Instruments. Now SRC has added a 2-1/2 year effort that combines and extends benchmarks at both NRI and STARnet to measure progress and compare the advantages and disadvantages of all the alternative approaches. The benchmark suite effort will be led by the Georgia Institute of Technology’s professor Azad Naeemi.
"We are looking at all alternative emerging devices that augment and complement complementary metal oxide semiconductors (CMOS) and field-effect transistors (FETs)," Naeemi told EE Times. "CMOS is approaching its scaling limit, therefore a global search is ongoing for alternative computing elements to complement the existing silicon infrastructure. Our research will compare all these options, their advantages, limitations and bottlenecks. And in fact, it may not be a single technology that dominates the future, but different device types might work well in different applications.
According to Tom Theis, executive director of SRC's NRI, the real benefit of the new benchmarking program will be to identify which of the alternative new devices have the most promise and why. The benchmarks will meet three design principles: to maintain compatibility with existing technology; to extend traditional devices with new types of technologies; and to extend methodologies that directly measure the advantages to be gained by each new type of device.
A smart scalable all-spin-detector circuit for low power non-Boolean pattern recognition, here showing a three pixel comparator unit cell. Credit: H. Aghasi and R.M. Iraei.
(Source: Cornel and Georgia Tech)
"We already have a family of traditional benchmarks--starting with standard logic functions, such and NAND and NOR, standard modules like adders and multipliers, as well as high-level functions like arithmetic-logic units (ALUs), but we now want to extend that family to encompass what new device types have to offer," Theis told EE Times. "We want to develop new benchmarks that extend to new functions, new ways of representing 1s and 0s such as spin, or many-body effects like phase transition or charge-density waves."
According to Theis, they have a long laundry list of new device types with new ones being added everyday, and want to help their supporters—IBM, Intel, Micron, and TI—get a leg-up on the ones most likely to succeed. With publications of their results coming later to the other SRC members, and the worldwide engineering community.
According to Naeemi, his group's goal will be to broaden the benchmarking base and improve engineers understanding of how each devices works and to which applications they might be most applicable.
"We want to highlight where researchers need to focus their efforts on how to take advantage of novelty, where improvements will be most effective, and not just for logic, but also for memory devices too," Naeemi told us. "It is extremely important to pull together and get an accurate overview of how each research effort is doing."
Switching-energy versus delay benchmark of a 32-Bit adder cast in next-gen technologies using tunneling, ferroelectrics, magneto-electrics and spin-torque technologies. Credit: Dmitri Nikonov and Ian Young.
Some of the most novel devices being benchmarked include transistor-like "steep slope" devices that operate at extremely low-voltages and thus very low power, non-volatile magnetic devices that unlike FETs can combine memory and logic functions as well as non-Boolean analog devices that "compute" like the neural networks of the human brain.
The benchmarking program will run through the end of 2017. Get all the details on SRC's Beyond CMOS Benchmarking site.
— R. Colin Johnson, Advanced Technology Editor, EE Times