In an effort to cover the waterfront of hot opportunities in IoT, automotive and other areas, TSMC showed several waves of specialty process it is now running or developing. They include ultra-low power versions of 55, 40 and 28nm processes debuting this year, a variant of its 16FFC next year and a possible 40nm process supporting 0.6V supplies in 2017.
The 55 and 40nm nodes target wireless microcontrollers and sensor hubs. The 16FFC variant should run at frequencies above a GHz, “certainly enough for high-end wearables,” said Sun.
The ULP nodes reduce supply voltages, extend Vt and sport SRAMs optimized for low leakage. Separately, TSMC will extend its processes for CMOS image sensors to include support for near-infrared imagers next year. In addition, it will expand its capabilities in CMOS MEMS to include MEMS microphones, gas and biometric sensors.
For car makers, the foundry plans a broad array of offerings possibly extending to 600V GaN and 2.5V 28nm nodes in 2019. Meanwhile it expects to support ADAS chips in its 20 and 16nm nodes by the end of next year. A 55nm embedded flash for car makers will be ready this year with a 40nm version supporting 1.5-2.5V operation coming in 2017.
TSMC is also working on specialty memories. An eRRAM device has been demonstrated supporting 100,000 write/erase cycles as an alternative to embedded flash. A 28nm eMRAM sing spin-torque transfer technology could be ready in late 2017 as another alternative.
In chip stacks, TSMC plans to be in production with InFO in 2017. It is suitable for integrating DRAM with cost-sensitive mobile and consumer chips on devices with less than 3,000 pins. One analyst said it will provide significantly more bandwidth and less power than today’s stacks that use wire bonding or flip chip packages.
InFO comes in two versions. One links a logic chip to DRAM memory; another version can stack multiple chips on top of another without a silicon interposer.
The technique requires new design tools such as links that connect separate databases for package and chip designs. Those tols should be ready by the end of the year.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times