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IBM Nanotubes May Redefine Future of Moore's Law

Switch to carbon at 3-to-5 nanometer
10/1/2015 03:01 PM EDT
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R_Colin_Johnson
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Re: Mixed Methods
R_Colin_Johnson   10/8/2015 11:02:50 AM
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Funny you should mention it--xprmntl--but I asked him if he was using CVD, and at first he said yes, but then he changed his tune in mid-sentence and said they deposeted them using PVD and high temperature annealing. Now I know why. Thanks for the careful reading of the Science paper. Great comment.

xprmntl
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Mixed Methods
xprmntl   10/7/2015 6:56:36 PM
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Shu-Jen Han is mixing his depositions techniques here: "

 

"We can place nanotubes in parallel with about a 8-to-10 nanometer pitch using self aligning techniques," Han revealed to EE Times. "We deposit them using a PVD [physical vapor deposition] process, then use high-temperature annealing--a metallurgical process akin to microscopic welding--to secure the channel contacts at each end."

 

According to the Science paper, patterned iron particles were to catalyze CVD for the aligned SWNTs, whiile PVD (Arc-Discharge) was used for the high quality SWNTs (which were then solution processed to sort and purify, and drop cast into random orientations).  And the 8-10 nm pitch is an average pitch, not a true periodic spacing of the CNTs. 

Spin, spin, spin.

 

R_Colin_Johnson
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Re: tunneling
R_Colin_Johnson   10/3/2015 12:25:58 PM
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Not acquainted with any tunneling problems, at least IBM mention none to me. Would you like me to ask them specifically, or were you just brainstorming? Thanks for the comment.

R_Colin_Johnson
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Re: tunneling
R_Colin_Johnson   10/3/2015 12:25:55 PM
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Not acquainted with any tunneling problems, at least IBM mention none to me. Would you like me to ask them specifically, or were you just brainstorming? Thanks for the comment.

R_Colin_Johnson
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Re: replace Finfet?
R_Colin_Johnson   10/3/2015 12:24:10 PM
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All I know is IBM told me their planar method worked better than finFETs at 9nm. Thanks for the comment.

resistion
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tunneling
resistion   10/3/2015 4:54:12 AM
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I think tunneling would be a problem for nanotube scale. Even from between the electrode contacts.

resistion
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Re: replace Finfet?
resistion   10/3/2015 2:47:06 AM
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5nm may be a gate-all-around vertical TFET.

R_Colin_Johnson
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Re: replace Finfet?
R_Colin_Johnson   10/3/2015 12:20:27 AM
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The way IBM explained it to me, was that they had known enginering work to be done before mass produdtion and gave two examples--getting their semiconutor nanotube sorting to 99.999 percent to get decent yields, and getting EUV working reliably at volume production speeds. They are shooting for 5 nanometer node-if all goes well-but if EUV is still not ready and/or nanotubers sorting doen't yet have enough 9s, then they will fall back to the 3-nanometer node.

resistion
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replace Finfet?
resistion   10/2/2015 8:01:37 PM
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Can it be brought in right after 10nm since 7nm is already considered post-silicon? Maybe 5nm is already too late?

R_Colin_Johnson
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Re: No competitive advantage
R_Colin_Johnson   10/2/2015 7:34:17 PM
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GroovyGeek; Are you saying that even though IBM has seemihngly surrmounted the sub-nanometer hurdlen for the post-silicon era, that it won't have a competitive adantage because it has too many patents on its technology. If so, IBM is willing to lisence its nanotube technology to others, especially now that they are fabless. If you are saying the other guys working together will be able to surrmont the sub-nanometer hurdle with silicon, then I respect your right to be hopeful about molecular-scale silicon gates, though it is not supported by any roadmap of which I know. IAC thanks for your optinion and comment. All are welcome at EE Times (except the profane) to express their opinioins. Thanks again.

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