SAN JOSE, Calif. – Marvell announced it is sampling its first products based on its MoChi approach to building modular SoCs. One of the two new 64-bit ARM processors also is the company’s first to implement its final-level cache (FLC) technology which aims to reduce the need for external DRAM.
MoChi is Marvell's approach to creating products that look like SoCs to applications software but may actually be composed of multiple die in one or more packages. The concept enables chips made in different processes to work together as closely as if they were on the same die.
The first two MoChi products sampling include Marvell’s AP806 which uses four ARM Cortex A-72 cores, supports FLC and will support multiple storage and networking companion modules. The other sampling MoChi product is the Armada A3700 which uses one or two Cortex-A53 cores along with future MoChi modules for connectivity and offload options such as packet processor offloads, Wi-Fi, BLE, ZigBee, USB, SATA, and more. Both new chips target a range of embedded systems especially in Marvell's core markets such as storage and communications.
The A3700 is Marvell’s first 64-bit Armada chip. The company had a 64-bit ARM line, the PXA family, mainly targeting mobile systems, but it canceled it.
A press release and Marvell’s Web site on MoChi provide few details on exactly what modules will be available when. Currently, Marvell is focused on using MoChi as a way to differentiate its own products and avoid the race to new and expensive semiconductor process nodes.
“The company is fully aligning to MoChi and all tapeouts will be MoChi enabled,” said Mordi Blaunstein, senior director, product marketing at Marvell.
MoChi modules connect via a version of ARM's AXI interconnect Marvell calls MCi. The company also created an enhanced coherent version of the link called Aurora2 to support use between die in one or multiple packages.
Marvell said the link supports coherent/non-coherent and packetized/serialized options including a short, reach 8 Gbits/second serdes. The interconnect is scalable in bandwidth and number of lanes it supports and can be used both within a die and between packaged chips. It does not require support from systems software.
A handful of Marvell products already support the MoChi interconnect.
Marvell chief executive Sehat Sutardja did much of the early engineering work on MoChi and FLC and announced the initiatives in a keynote at an industry event in January.
Sutardja pitched MoChi as a way to get around the increasing costs of using advanced process technologies. In the Marvell press release, analyst Linley Gwennap was bullish on the concept.
“The introduction of Marvell’s AP806 MoChi module is the first step in creating a new process that can change the way that the industry designs chips,” said Gwennap in the release. “This Virtual SoC is a simpler, more flexible approach that can reduce design cost and speed time to market,” he added.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times