ISSCC also will describe advances in several application areas from fingerprint recognition to machine vision and DNA sequencing
A team from Invensense and the University of California will describe an ultrasonic fingerprint sensor using “a 110×56 PMUT array bonded to a CMOS chip that delivers a 431×582 dpi image in 2.64ms while consuming just 280μJ.
“Its unique ability to image both the surface epidermis and sub-surface dermis fingerprint make it insensitive to perspiration and resistant to spoofing, enabling highly robust, low-cost personal ID sensing” in mobile devices, ISSCC organizers said.
Researchers in Korea and the U.S. will present papers on chips for advanced machine vision.
Korea’s KAIST will describe “best-in-class accuracy in an audio-visual interface for smart glasses through integration of a [65nm] multicore deep learning processor,” the ISSCC program said. It delivers “a 56.5% power efficiency improvement over the latest processor [for head-mounted displays], and ~2% higher recognition rate over the best-in-class pattern recognition processor,” it added.
Researchers from MIT will deliver two papers on machine vision. One describes the “first reported efficient deep-learning processor…capable of flexibly mapping state-of-the-art deep neural networks.” The 65nm chip is a “deep convolutional neural network accelerator featuring a spatial array of 168 processing elements fed by a reconfigurable on-chip network [that] supports state-of-the-art CNNs, such as AlexNet, and is over 10× lower power and requires 4.7× fewer DRAM access per pixel than a mobile GPU,” the ISSCC program said.
Separately, other MIT researchers will present a paper on a 3-D vision processor that uses data from a time-of-flight camera to create a navigation device for the visually impaired. It detects safe areas and obstacles at 30fps, and consumes just 8mW from a 0.6V power supply.
Advanced vision chips will serve a market for smart glasses and displays expected to grow to $120 billion business by 2020, organizers said. They also will find use in autonomous cars and drones, they added.
Intel will deliver several papers at the event, perhaps the most intriguing of which is one co-authored by University of California researchers on a proof-of-concept device for DNA sequencers. The 32nm chip integrates an 8,192-pixel nanogap transducer array on to CMOS readout circuits to create an “electrochemical bio-sensing technique for DNA sequencing leveraging CMOS scaling while achieving high signal-to-noise ratio.”
“Existing solutions for DNA sequencing either employ optical sensing techniques that are difficult to scale or molecular sensing methods that have low SNR,” said ISSCC organizers. “The proposed method paves the way towards smaller, lower cost DNA sequencing that can be integrated with electronics,” it added.
Finally, Mediatek will present the “industry’s first tri-cluster, 10-core CPU, featuring three ARMv8a CPU clusters optimized for 1.4GHz, 2.0GHz, and 2.5GHz operation in a 20nm high-κ metal-gate process. Compared to dual-cluster CPUs, the addition of a third cluster provides 40% higher overall performance with 40% improved power efficiency,” the program said.
“Simply adding more cores doesn't necessarily improve the processor,” said analyst Kanter.
“In a big.little configuration, I can easily understand when the power manager should use a little core, and when it should use a big core,” he said. “The question I'd wonder is whether the gap between the big and little cores is sufficiently large to merit an intermediate option, and how the power management will exploit those cores,” he added.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times