TORONTO—What's after DDR4? Hybrid Memory Cube (HMC) or High Bandwidth Memory (HBM)? Right now, it's not clear, so for now all have opportunities to find uses in a variety of computing scenarios.
The Hybrid Memory Cube (HMC) specification has been out for more than a year, and products are starting to hit the market, albeit not in high volume. HMC was initially announced by Micron in 2011; the majority of vendors releasing products that use HMC are part of the HMC Consortium, which was founded in October of the same year.
Highlights of the HMCC 2.0 specification included increased data-rate speeds, from 15 Gbit/s in 1.0, up to 30 Gbit/s, and migrating the associated channel model from short reach (SR) to very short reach (VSR) to align with existing industry nomenclature. HMC uses a vertical conduit called through-silicon via (TSV) that electrically connects a stack of individual chips to combine high-performance logic with DRAM die. The memory modules are structured like a cube, instead of being placed flat on a motherboard, allowing dramatic performance improvements over DDR4 with lower power consumption.
HBM, meanwhile, is a high-performance RAM interface for 3D-stacked DRAM memory from AMD and SK Hynix for use in conjunction with high-performance graphics accelerators and network devices.
While development of HMC has been driven by the predicted limits of DRAM, "it's not hitting the wall that quickly," observed Jim Handy, principal analyst with Objective Analysis, in a telephone interview with EE Times. DDR4 is only beginning of its lifecycle, he added, and DRAM standards tend to last around six years.
But what's important, Handy said, is that the path beyond DDR4 is not well-defined. "HMC is an alternative to the complete lack of a roadmap for the next generation of DDR." Given that HMC and HBM products are rolling out along with DDR4, it's clear there's room for all three technologies to find market share as standards take time to settle into place.
Intel's latest-generation Xeon Phi co-processor uses HMC stacked memory technology.
One of the most recent HMC-related products to launch is Intel's latest-generation Xeon Phi co-processor with 72 individual cores manufactured on the company's 14nm Tri-Gate Transistor process. It uses Multi-Channel DRAM (MCDRAM) memory, created in partnership with Micron and based on the companies' co-developed HMC stacked memory technology. Using MCDRAM, Intel has boosted memory throughput by around 50% compared with planar GDDR5.