This article is part of EDN and EE Times' Hot Technologies: Looking ahead to 2016 feature, where our editors examine some of the hot trends and technologies in 2015 that promise to shape technology news in 2016 and beyond.
Nanotube research has been ongoing since 1991, when they were first discovered by researcher Sumio Iijima at NEC (Japan). He described nanotubes as the fourth form of carbon, after graphite, diamonds and fullerenes (Buckyballs). Consistently measuring about 1.2 nanometers in diameter (for the single walled variety) they are essentially atomically thin layers of graphene rolled into tubes.
Nanotubes were almost immediately identified as a possible replacement for the channel in silicon transistors, because their electron mobility is in excess of 100,000-cm2/volt-second at room temperature—over 70 times faster than the 1,400-cm2/V-s mobility of standard silicon chips.
Different methods were tried to place pre-made nanotubes across the source and drain of a silicon transistors, and secondly to use a seed placed atop the source and drain and try to grow them in place. Such attempts have been made by labs around the world repeatedly from 2002 to 2015 but none have been as successful as placing pre-made nanotubes.
Postdoctoral fellow Wenzhuo Wu (left) and Professor Zhong Lin Wang (right) at Georgia Tech propose molybdenum disulfide as the wonder materials to replace silicon because it is extremely light, bendable, stretchable and piezoelectric. (SOURCE: Rob Felt, Georgia Tech)
Nanotubes are easy to make by mechanical methods, but unfortunately some are metallic instead of semiconducting—due to their chirality—making it essential to find ways to eliminate the metallic kind which would just short-out a transistor. Two methods have been successful developed, one sorting them ahead of time and the second burning out the metallic ones after placement with a high-voltage pulse, like opening a fuse.
3-D chip from Stanford connects four layers with standard vias, with the bottom being standard CMOS, the top being carbon-nanotube logic transistors, and the middle two layers of resistive random access memory (RRAM). (SOURCE: Stanford University, Mitra/Wong Lab)
Once that problem was solved, the last problem became how to put them where you want them—as channels—on a silicon substrate. At first they were merely placed randomly, with little success, but in 2015 IBM reported a successful auto-alligment method for placing them across the source and drain, using as many of them as is necessary in parallel to carry the current needed.
A diagram showing IBM's fabricated nanotube transistor with an end-bonded contact and a contact length below 10-nanometer. (SOURCE: IBM Research)
Transmission electron microscope (TEM) Cross-sectional image showing the fabricated nanotube transistor with an end-bonded contact. (Source: IBM Research)
The graphene researchers have not given up—in fact Texas Instruments is now capable of growing wafer scale graphene and the Chinese have taken the lead in developing both graphene and nanotubes according to Lux Research.
"Aggregate current capacity of Chinese carbon nanotube suppliers can meet forecasted global demand until 2015," according to Lux Research Analyst Zhun Ma. But in 2016 demand will outgrow China's capacity to supply, providing yet another reason that this is the year of the nanotube transistor.
- FinFETs with III-V Channels: While nanotubes provide the fastest channel material available today, III-V materials like gallium arsenide (GaAs) and indium gallium arsenide (InGaAs) are all being explored by IBM, Intel, Imec and Samsung as transistor channels on silicon substrates. In fact, just this year Imec and IBM both reported similar methods of successfully doing so. IBM's called confined epitaxial overgrowth—or CELO—merely grows a thin oxide on a silicon wafer, then etches trenches down to the silicon where ever it wants a transistor channel. It then grows the III-V material from the trench—acting as a seed—without the lattice mismatch problems that would plague growing III-V on silicon.
- 2-D Black Phosphorus Beats Carbon: Dozen of researchers worldwide are experimenting with black phosphorus as an alternative to nanotubes and graphene for the next generation of semiconductors. Black phosphorus has the advantage of having a bandgap and works well alongside silicon photonics devices, which are also skyrocketing in popularity.
- 3-Molybdenum disulphide MoS2 is also a contender for the next generation of semiconductors, due to its novel stacking properties. For instance, a single layer of it is a normal semiconductor, but add a second layer and it become piezoelectric (likewise even numbers of layers is piezoelectric and any odd number of layers is not). The team of Professor Zhong Lin Wang and postdoctoral fellow Wenzhuo Wu are building a new type of transistor with it at Georgia Tech.
— R. Colin Johnson, Advanced Technology Editor, EE Times
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