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Google, HP, Oracle Join RISC-V

Open source processor core gains traction
12/28/2015 08:00 AM EST
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eaglewhite
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HPE, not HP
eaglewhite   1/3/2016 5:27:23 PM
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Hi, IMHO if it's Hewlett Packard Enterprise that's involved - the title should state HPE, not HP. Otherwise it is a bit misleading. ;)

 

GSMD
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Re: out-of-order
GSMD   12/28/2015 10:57:33 PM
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1. Actually RISC-V supports 32, 64 and 128 bit adress spaces. There are actually two reserach efforts that are using the 128 bit option. So it is not a "only on paper" feature ! Useful for memory mapped sparse address spaces that storage folks use.

2. OO is orthogonal to the ISA but RISC-V does make OO much easier to implement. Not having artifacts like condition codes makes a micro-architceture designer's life a lot easier. Two OO implementations have been released.

rick merritt
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Re: out-of-order
rick merritt   12/28/2015 9:43:26 PM
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Thanks for the clarification

_cpc_
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out-of-order
_cpc_   12/28/2015 4:04:55 PM
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Nice article Rick.

 

> The RISC-V instruction set supports 32- and 64-bit designs as well as vector and out-of-order extensions.

 

One point of clarification though - there's no out-of-order extension. Rather RISC-V doesn't make OoO difficult to implement.

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