Three papers will describe FPGA-based accelerators using embedded RISC-V cores, a hot area given work by Web giants such as Microsoft and Baidu on FPGA accelerators.
Jan Gray, a former software architect on a Microsoft parallel computer, will describe an FPGA accelerator using RISC-V cores. Guy Lemieux, an academic and chief executive of VectorBlox Computing, will describe a similar project.
ROA Logic, an FPGA and ASIC design services company in the Netherlands, will describe various RISC-V implementations.
“I was surprised by how many people are getting involved -- we’ll be sold out with about 130 people,” said O’Connor. “You’ll see folks developing products that cover the waterfront from embedded to high-end server-class processors -- initial [commercial] products will be lower-end embedded SoCs,” he added.
The RISC-V instruction set supports 32- and 64-bit designs as well as vector and out-of-order extensions.
Even if it gains significant traction, RISC-V is not likely to have any major impact on ARM and Mips, given those vendors are well established with broad sets of customers and partners. However, the architecture could enable a new class of designs from small teams that would otherwise lack the heft to design their own chips.
"Open source has worked well in the software community, so there’s a place for this type of effort in CPUs but there’s a lot of practical issues they have to overcome, and I wouldn’t see this competing with ARM anytime soon,” said Linley Gwennap, principal analyst of the Linley Group (Mountian View, Calif.).
The lack of support is the biggest challenge ahead for anyone adopting RISC-V. “Open source software spawned business models for providing support, and that’s probably what will have to happen here,” Gwennap added.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times