The good news for RISC-V is it has attracted a core of seasoned engineers enthusiastic about the project’s potential. For example, Jon Masters, chief ARM architect for Red Hat, took a vacation day to attend the workshop and volunteered to lead a key task group defining a platform specification.
Masters said hopes to write a book about porting Linux to the first commercial open source core. Others said the event marked a historic moment in what will likely be a ten-year process to establish a free microprocessor, disrupting the semiconductor industry in ways Linux upended the software world.
“Everyone wants a free Linux core,” said Andreas Olofsson, chief executive of semiconductor startup Adapteva, who joined the fledgling platform working group.
In today’s cost-squeezed environment, any company would adopt a free control core then try to create differentiation in software or other hardware blocks, said Olofsson who sported a beard that is a sign he is well along in working on his next-generation Epiphany processor.
Engineers from small companies say they cannot afford the several million dollars required to license an ARM core, several weeks to negotiate the license and a man-year of engineering to integrate it into an SoC. Using roughly similar engineering resources, they can modify RISC-V to suit their needs, something not allowed under a standard ARM license, Olafsson said noting Adapteva is already contributing to and drawing from open-source hardware efforts.
Bigger companies are already kicking the tires. For example, the chief technologist of Chelsio and a member of Microsoft’s silicon group attended the event.
“I could see how pretty quickly a RISC-V core could be useful for something simple like a security processor that doesn’t need to run a full operating system,” said Eric Mejdrich, a principal hardware architect from the group developing chips inside the Xbox and HoloLens.
For companies willing to accept some risk, the cores could be ready to use in commercial chips within a year, according to one engineer whose company is evaluating RISC-V and asked to remain anonymous. For more risk averse companies, it could take up to three years, he said.
In a sign of the breadth of interest in RISC-V, Oracle, who hosted the workshop in a theater at its headquarters here, had six engineers signed up to attend the event including the vice president of Oracle Labs. Eight engineers signed up from AMD, the most from any one place except UC Berkeley which gave birth to the initiative in August 2014. Other attendees came from companies including ARM, Ceva, eASIC, Lattice, Huawei, IBM and Nvidia.
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