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Free Core, Some Assembly Required

RISC-V rallies engineers for open hardware
1/7/2016 07:50 AM EST
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adapteva
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Additional observations
adapteva   1/7/2016 9:30:32 AM
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Rick, great article as usual!

A couple of additonal observations.

1.) The "google engineer' is Ron Minnich the founder of Coreboot.

https://en.wikipedia.org/wiki/Coreboot

2.) To me the highlight of the conference was the presentation on the 2nd day showing the world's first microprocessor (RISC-V) with integrated optical interconnects that was published in Nature. An incredible example of what open collaboration can achieve!!

https://aspire.eecs.berkeley.edu/2015/12/risc-v-based-photonic-processor-in-nature/

GSMD
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India Processor Effort
GSMD   1/7/2016 12:10:36 PM
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The Indian effort got funded two years ago and two cores have been released as open source cores. Wonder who told you that funding will start only in March ! If you need more info on this effort, please ask me, I am the tech lead. Full SoCs will be released by summer. Please see bitbucket dot org slash casl. We are probably also the only risc v effort targetting the high end server market.

pattrsn
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Re: Additional observations
pattrsn   1/7/2016 1:50:50 PM
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Here is link to Nature article on optical RISC-V:

http://www.nature.com/nature/journal/v528/n7583/full/nature16454.html

perl_geek
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Siblings, not derivatives
perl_geek   1/7/2016 1:58:45 PM
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I'm not sure who would be more offended by your description of FreeBSD as a "Linux variant"; the BSD people or the Linux people.

Though both descend from and embody The One True Religion (Unix), they are entirely separate bodies of code, with different histories and licenses. Enlightenment has many paths. :-)*

 

pattrsn
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RISC-V core in 350 LUTS!
pattrsn   1/7/2016 2:03:29 PM
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While there were many impressive presentations, the highlight for me was Jan Gray's "GRVI-Phalanx" that fit ~400 RISC-V cores onto a single FPGA.

Each runs at >300 MHz and needs only 350 LUTS. Stated alternatively, he is able to deliver 1 million instructions per second per LUT, which must be a new world record. Note even less ambitious processor cores take ~2000 LUTS and run at ~100-150 MHz.

This achievement is a testament to both the Gray's engineering poweress and the simple elegance of RISC-V.

rick merritt
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Re: India Processor Effort
rick merritt   1/8/2016 12:55:00 AM
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@GSMD: Thanks for the url. Let's talk.

krste
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RISC-V is not a free core, it's a free and open ISA
krste   1/8/2016 4:56:36 AM
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Hi Rick,

Thanks for great coverage of the event.

I just wanted to clarify for your readers that RISC-V is not an open-source core - it's a free and open ISA specification around which a whole ecosystem is being built.

Of course, there are now many open-source RISC-V cores available, and not just from Berkeley.

But there are also quite a few proprietary RISC-V cores in various stages of development, most of which will probably never be publicly announced.

 

modal
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Re: RISC-V core in 350 LUTS!
modal   1/8/2016 2:55:19 PM
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Are the videos going to be placed online again?

http://riscv.org/workshop-jun2015.html

http://riscv.org/workshop-jan2015.html


Didn't see the second seminar till just now.

krste
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Re: RISC-V core in 350 LUTS!
krste   1/8/2016 7:29:12 PM
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Yes, both slides (soon) and video (later) as before.

 

ronaldgminnich
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slight correction on my coreboot talk
ronaldgminnich   1/10/2016 1:31:53 PM
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Hi, I enjoyed the article, but I do have a slight correction.

Coreboot runs on all Chromebook and Chromebox devices. There no Android devices that I know of running coreboot.

Coreboot runs on the RISCV simulators and has for 15 months, booting to Linux. We are hoping to have it on RV64G hardware as soon as we can get some :-)

There are no available RISCV Chromebook/box devices and I am sorry if I left that impression.

Thanks!

ron

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