RISC-V rallies engineers for open hardware
REDWOOD SHORES, Calif. – It’s early days for RISC-V -- an open specification seen as a Linux of microprocessors. On its long to-do list, engineers still need to define basic pieces of the instruction set architecture including its memory model, how it will speak to the external world of I/Os and how to debug it.
Many of the about 150 developers who signed up for the third RISC-V workshop volunteered to start a handful of working groups to address the most pressing issues in fundamental areas including security, virtualization and compliance. Proponents said the effort has taken the vanguard of the open source hardware movement, attracting leaders of earlier OpenCore and OpenRISC efforts.
The LowRISC project at the University of Cambridge is attracting interest as the likely first source of real development hardware. The team which includes members of the Raspberry Pi project hopes to have first silicon this year and plans to make development boards available in 2017, likely for $50-100.
The first of several planned LowRISC chips will tape out before the end of the year, a 9mm2 28nm part that fits in BGA package. It will use four cores running at more than a GHz with 512 Kbytes L2 cache and a 32-bit LPDDR3 memory controller. The group ultimately aims to deliver a low-cost board made completely with open source digital logic.
LowRISC expects to use up to four RISC-V cores at Raspberry Pi prices. (Image: Cambridge University; All pictures courtesy Krste Asanović)
Until LowRISC is available, developers will work with a handful of emerging system simulators and soft cores mainly implemented in FPGAs. One engineer said he is 80% done with a QEMU emulator for RISC-V that could be completed in two weeks.
Such tools will be key for the biggest job ahead, creating a software ecosystem for RISC-V. Ports of a handful of Linux variants including FreeBSD are well underway as are other low-level components, but ports of more widely used RTOSes and Android are more than a year away.
Ultimately, the effort must attract the broader world of applications developers if it is to become commercially significant. “We need more developers and more documents and specifications to reduce their startup costs,” Arun Thomas, an R&D engineer at BAE Systems told attendees.
So far, 48 individuals from seven universities and companies including BAE, Bluespec, Google, LG Electronics and Vectorblox have made software contributions to RISC-V on GitHub. Thomas rattled off a laundry list of needs ranging from specs for direct-memory access, an I/O memory management unit, performance counters, an applications binary interface, bootloaders, hypervisor and security extensions as well as the kind of detailed programming guides ARM provides its users.
“There’s a fair amount of work ahead just on the spec side,” Thomas said.
A basic port of FreeBSD was created from scratch with 25,000 lines of fresh code written in the last six months, reported Ruslan Bukin, a researcher at the University of Cambridge. This year the group aims to add support for multicore architectures, floating point units, Ethernet drivers and expanded virtual addresses.
Next page: Engineers take arms against ARM
Small companies seek ARM alternative
The good news for RISC-V is it has attracted a core of seasoned engineers enthusiastic about the project’s potential. For example, Jon Masters, chief ARM architect for Red Hat, took a vacation day to attend the workshop and volunteered to lead a key task group defining a platform specification.
Masters said hopes to write a book about porting Linux to the first commercial open source core. Others said the event marked a historic moment in what will likely be a ten-year process to establish a free microprocessor, disrupting the semiconductor industry in ways Linux upended the software world.
“Everyone wants a free Linux core,” said Andreas Olofsson, chief executive of semiconductor startup Adapteva, who joined the fledgling platform working group.
In today’s cost-squeezed environment, any company would adopt a free control core then try to create differentiation in software or other hardware blocks, said Olofsson who sported a beard that is a sign he is well along in working on his next-generation Epiphany processor.
Engineers from small companies say they cannot afford the several million dollars required to license an ARM core, several weeks to negotiate the license and a man-year of engineering to integrate it into an SoC. Using roughly similar engineering resources, they can modify RISC-V to suit their needs, something not allowed under a standard ARM license, Olafsson said noting Adapteva is already contributing to and drawing from open-source hardware efforts.
Bigger companies are already kicking the tires. For example, the chief technologist of Chelsio and a member of Microsoft’s silicon group attended the event.
“I could see how pretty quickly a RISC-V core could be useful for something simple like a security processor that doesn’t need to run a full operating system,” said Eric Mejdrich, a principal hardware architect from the group developing chips inside the Xbox and HoloLens.
For companies willing to accept some risk, the cores could be ready to use in commercial chips within a year, according to one engineer whose company is evaluating RISC-V and asked to remain anonymous. For more risk averse companies, it could take up to three years, he said.
In a sign of the breadth of interest in RISC-V, Oracle, who hosted the workshop in a theater at its headquarters here, had six engineers signed up to attend the event including the vice president of Oracle Labs. Eight engineers signed up from AMD, the most from any one place except UC Berkeley which gave birth to the initiative in August 2014. Other attendees came from companies including ARM, Ceva, eASIC, Lattice, Huawei, IBM and Nvidia.
Next page: Google, HPE provide soft support
Google, HPE provide soft support
At the workshop, software experts from Google and Hewlett-Packard Enterprise (HPE) described work porting to RISC-V firmware stacks they are trying to establish as industry standards.
A Google engineer said the company has its Coreboot now running on RISC-V. The firmware is embedded in Chromebooks and Chrome-based media-streaming systems using other processors. He also called for help porting to RISC-V Google’s Go programming language, a project a three-person team at Google has already started.
HPE has cobbled together a rough port of the UEFI firmware used in x86 PCs and servers. RISC-V lacks power management, trusted mode and systems management specifications, said Abner Chang, an HPE software engineer working on the UEFI port. Microsoft also needs to fill in key pieces of the UEFI port, he added.
Chang made a special plea for a management mode to enable the free core to achieve its full potential. “RISC-V is not just for embedded systems, we can bring it to PCs and servers,” he said.
Another HPE engineer reported on a breakout group on defining the RISC-V memory model. “Memory subsystems are generally getting more complex…the feeling was there’s a lot of work to be done in this space,” he said, noting the potential to borrow many concepts established by x86 and ARM chips
A separate security group parsed out a wide range of topics RISC-V could address. The effort has already attracted attention and support from both the U.S. and India governments for national security projects.
Draper Labs is developing a RISC-V chip using metadata to tag memory addresses with security policies, a concept developed in a secure computing program sponsored by DARPA last year.
In India, the Modi government has approved a budget that includes funding for a national microprocessor development project. Work could start as early as March when funding starts to flow to the effort that aims to create a family of RISC-V-based processors that would be available for military systems as well as commercial users in India.
Jan Gray described the Hoplite network-on-chip he is developing.
A handful of papers presented projects using RISC-V as an embedded core in an FPGA that acts as an accelerator for various applications. For example, former Microsoft researcher Jan Gray described an FPGA using 400 RISC-V cores delivering nearly 100,000 Mips.
Gray’s design, which he was able to boot on Christmas Eve, uses a novel network-on-chip with a compact router making it easier to place and communicate with cores in a large array. “This router will change the way people design large FPGAs,” he claimed of the design he has yet to complete and aims to license.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times