SAN JOSE, Calif. — Extreme ultraviolet lithography is making slow progress, re-kindling hopes it could be ready for production use in the 7nm node. The semiconductor industry has placed multi-billion dollar bets the technology will someday help make smaller, cheaper chips but critics are still skeptical.
So far, EUV lacks a powerful and reliable enough light source to produce the number of wafers per day today’s chip plants require. ASML, which makes the systems, gave a progress report at the Industry Strategy Symposium last week and one of its customers, TSMC, is expected to provide more data in a talk in late February.
Prototype systems installed at commercial fabs such as TSMC now use an 85W light source, soon to be upgraded to 125W. ASML recently demoed an 185W capability and promises it will hit 250W before the end of the year.
ASML demoed an 185W EUV system but production systems need a 250W light source. (All images: ASML)
Systems are running as much as 70% of the time, putting out 500-600 wafers/day. That’s a big step from where EUV was a year ago, but still far from the throughput of today’s machines using less refined immersion technology.
“We are a factor of 2-3 out from where we need to be,” said Frits van Hout, chief program officer for EUV at ASM at the event hosted by the SEMI trade group. Currently shipping prototype tools “will need to be field upgraded to be fully ready, but I would guess by the end of this year we should be at that point,” he added.
Chip makers currently hope they can start using EUV machines in production flows by sometime in 2018. At that point they would help lower cost for a second-generation of 7nm chips.
The good news is EUV is highly accurate with systems hitting some targets within fractions of a nanometer. But given the many delays around throughput and reliability it may require an upgrade of its numerical aperture to be of use at 5 or 3nm line widths. ASML is “discussing details with stakeholders of the configuration and timing of [such a] machine…we are taking steps to make it possible,” he said.
Van Hout showed the layout of a DRAM fab using EUV, claiming the technology could improve the plant’s throughput and raise yields 7-9% by reducing process steps 29-32%. Today’s immersion systems need to expose wafers multiple times to achieve the fine lines required at 16nm and smaller nodes.
TSMC reported a peak in EUV uptime and a current average in throughput.
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