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Moore’s Law Goes Post-CMOS

2/1/2016 03:00 PM EST
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JonD9
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Re: Definition please
JonD9   2/4/2016 6:55:55 PM
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@srikhi, I think "vanilla" was intended to refer to CMOS in contrast to more "exotic" device types. CMOS is indeed much more complicated than it used to be.  While we have used complementary MOSFET devices to compute for the past few decades, and now researchers are considering using transistors with fundamentally different physics (see the figure for some of the options).  Changing device physics can require changes to circuit architecture and more.  If 1 new transistor replaces on average 2 CMOS transistors then Moore's Law marches on without even changing the number of transistors.

srikhi
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Re: Definition please
srikhi   2/3/2016 1:13:18 PM
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Thanks @rick. Today's vanilla is yesterday's chocolate flavor. I see Moore's Law pursuit as a continuum with a nonlinear curve representing increasing difficulty and innovation. This is why I have some difficulty with the relatively simple model of TODAY-Vanilla-TOMORROW-PostCMOS. Over the last two decades, we have seen an explosion in the number of elements used from periodic chart, we have stretched and strained the lattice,  We have replaced the gate oxide with metal, we have abandoned the planar transistor architecture in favor of flowing current around three dimensional gates, we made dry lithography wet, and we learned how to strike the right balance between structural strength of the metal stack and its low-K dielectric properties. All of this has resulted in a consistent reduction of cost-per-transistor (CPT) at each node of Moore's law from 180nm down to 14nm.  Looking to the future there is a pipeline of innovations some of which have been cooking for a while and some of which are being added in real time. The key for the semiconductor industry is that we stay focused on CPT reductions (because they are at the core of Moore's Law promise) as we navigate our way through the pipeline. 

rick merritt
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Re: Definition please
rick merritt   2/3/2016 12:10:53 PM
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@srikhi  Good question. I am borrowing Holt's categories of today's CMOS broadly (as "vanilla") and a basket of techniques he mentioned including tunnelling FETs, ferro FETs, spintronics and etc as Post-CMOS

srikhi
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Definition please
srikhi   2/3/2016 2:12:17 AM
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Rick, You use phrases like Vanilla CMOS and Post CMOS in this article. Just what do those terms mean? 

resistion
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Re: EUV
resistion   2/2/2016 11:53:49 PM
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It's pretty much accepted that EUV would be used as one of the multipatterning exposures for a given layer pattern. So I wouldn't say it reduces the need for multipatterning, but the number of exposures. But an EUV exposure currently is more expensive and troublesome than a few 193 nm exposures. For this reason, leading companies do not wait for EUV to go to the next node, but directly add on the extra exposures using immersion lithography.

alex_m1
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Re: EUV
alex_m1   2/2/2016 2:36:01 PM
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Rick : the options on this illustration don't seem too far from CMOS. Will they suffice to solve the heat problem of 3D semi ?

 

And if not , maybe the only reasonable choice is tunneling transistor , like shown in :

http://www.eetimes.com/document.asp?doc_id=1327650

 

rick merritt
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Re: EUV
rick merritt   2/2/2016 12:28:30 PM
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@dglover: He implied that saying Intel "hasn't given up hope EUV could be inserted into the 7nm flow" sometime after first production of 7nm starts

dglover
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EUV
dglover   2/2/2016 10:27:52 AM
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Did Bill Holt say that EUV wouldn't be ready for the beginning of Intel's 7nm introduction?

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