SAN FRANCISCO – Moore’s Law has a long life, but pure vanilla CMOS process technology -- not so much. That’s the view of Intel’s top fab executive, speaking to an audience of chip designers.
“The economics of Moore’s Law are sound if we focus on reducing cost per transistor,” William Holt told about 3,000 attendees of the International Solid-State Circuits Conference (ISSCC) here. But “beyond CMOS we’ll see changes in everything, probably even in computer architecture,” he said.
The general manager of Intel’s technology and manufacturing group declined to share his thoughts about which of a “rich variety” of post-CMOS technologies chip makers will use or when. New techniques span tunneling FETs, ferroelectric FETs, spintronics, new III-V materials and more.
Holt did assert the new techniques won’t be in Intel’s 10nm process in which Intel is now prototyping its next-generation processors. In general, engineers will stretch CMOS as far as possible. Longer term, chips will be hybrids of different techniques blended with traditional CMOS.
“We will see a mixed mode operation…parts [of the wafer] with CMOS and new devices on same wafer optimized for different benefits,” he said.
Holt put a positive spin on what is clearly a huge research effort ahead blazing a path for semiconductors in the next decade.
“I can’t tell you which of these [post-CMOS] technologies will be first or best but when we see this richness [of possibilities]…that provides a wealth of opportunities over the next few years to make the tremendous progress needed in how to architect our parts,” he said. “It’s your challenge to figure out how to make them,” he told attendees.
The big challenge is that so far all the post-CMOS alternatives help reduce power consumption, a top concern, but they also run significantly slower than CMOS circuits. Holt compared this problem to the new complexity CMOS required a generation ago when engineers shifted to it from bipolar, responding to pressing power needs of the time.
A wide variety of post-CMOS technologies can lower power, but they cause delays. (Charts courtesy of Intel, ISSCC))
Holt said the industry needs to keep a focus on keeping power down and reducing cost per transistor. He reiterated Intel’s claim it has reduced cost per transistor at its 22 and 14nm nodes at a rate slightly better than the industry’s 30% historical trend. That’s despite the fact the cost of developing each new process has risen to 30% in the last few nodes up from a historical trend of 10%.
“It’s too early to make a prediction on the details of the 7nm node, but we can say we may be more in the range of the historical line of cost per transistor reduction at 7nm -- but we see a feasible path to cost reduction,” he said.
After his talk, Holt clarified that predictions of Intel’s 7nm node currently fall in a range extending from the historical cost/transistor reductions to the slight improvements Intel reaped at 22 and 14nm. “Lots of things are still up in the air, so we don’t know where we will fall in that window,” he told EE Times after his keynote.
Intel has not given up hope it may be able to start using extreme ultraviolet lithography sometime after 7nm production begins. EUV could have a significant impact on 7nm costs, reducing the need for multi-patterning.
Separately, Holt noted Intel’s 10nm process will support five voltage threshold levels. The variety of optimization points in a given node will likely increase as post-CMOS technologies are added to the mix.
Power options are increasing, said Holt, noting the low power version of Intel's upcoming 10nm process will support five voltage thresholds.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times