SAN FRANCISCO – Micron described a novel flash design that on paper beats the vertical NAND technology Samsung has been using to drive its leadership in non-volatile memory. The two gave competing presentations at this week’s International Solid-State Circuits Conference (ISSCC) that entertained and stumped even veteran flash-memory gurus.
Micron showed a 768 Gbit 3D NAND device using three-bit/cell floating gate technology. It tucked control circuits under the flash array to deliver a density of 4.29 Gbits/mm2 compared to 2.6 Gb/mm2 for the most dense 256Gbit 3D NAND chip Samsung ships today. By contrast, the planar NAND chips most companies currently sell pack just 1 Gbit/mm2.
Executives at Micron have not yet decided whether they will commit to manufacturing the design as a product, Tomoharu Tanaka, a Micron fellow and author of the paper told EE Times.
Floating gate technology has long been popular in planar flash design. Samsung and others used a different approach called charge trapping in 3-D NAND devices which is in some ways simpler to build.
Micron's floating gate design hit a new high in reported 3D NAND density. (Images: ISSCC)
“From the 1990’s to now the industry choose lower cost rather than high performance [architectures for NAND], now we enable both simultaneously,” Tanaka told a packed room of engineers here.
The Micron chip is relatively large at 179.2mm2 compared to 97.6mm2 for the Samsung device. “There have been many other NAND chips that size, though, so its size is not a show-stopper,” said Jim Handy of Objective Analysis (Los Gatos, Calif.).
The Micron part has much faster read times at 800 Mbytes/s compared to 178 Mbytes/s for Samsung. However the Korean giant wins on write times at 53 Mbytes/s compared to 44 Mbytes/s for Micron.
To date, all 3-D NAND chips use charge traps but it is a relatively expensive approach compared to floating gate technology used in most planar flash.
“I am skeptical of the industry’s ability to make [charge-trap based] 3D NAND cost competitive with planar NAND,” said Handy. “Perhaps Micron’s floating gate products will turn that situation around, but it’s too early to tell,” he said.
Samsung has a lead in the flash market with a 34.1% share followed by Toshiba, SanDisk and Micron in fourth place with a 14.6% share.
“Samsung is ramping V-NAND aggressively, hoping that volume will help them to get over the significant hurdles facing this technology…It’s also helpful for their image as a technology leader, but this is an expensive way to prove that point,” said Handy.
Toshiba/Sandisk have 768 Gbit TLC 3D BiCS on their road map for late 2017 and a 1Tbit chip for 2018, noted Alan Niebel of Webfeet Research (Monteray,Calif.)
The Micron architecture may have at least one Achilles heel. It currently uses relatively large 96 MByte blocks and does not enable a partial block write or erase operation. “I’m not so familiar with the systems side [of the business], but I believe many apps can access this block size although some don’t,” Tanaka said in response to a question from a SanDisk engineer.
Next page: The jury is out, says flash pioneer