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Micron, Samsung in Flash Battle

768 Gbit Micron chip beats Samsung’s V-NAND
2/5/2016 08:00 AM EST
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CC VanDorne
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The limitations of the planar process...
CC VanDorne   2/25/2016 2:51:36 PM
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...are such that it has tapped out at 16nm.

So naturally when you can't cram any more cubicals onto a sinlge-floor building that sits on a limited peice of property its then time to build more floors, or stories, to the building.  No brainer.  But I am surprised at how many more stories these guys are shooting for - 24, 32, 48?  Wow, that's ambitious!  Why not just two 28nm layers, and make it work fantacstically?

And then there is the question of cost: if we've now added a third dimension (36 layers of it) calculating success in terms of Gb/mm^2, or Tb/in^2 seems kind of moot, no?  Silly, at least, correct?  Maybe I'm missing something but shouldn't we now be more intersted in Gb/mm^3 and Tb/in^3?

 

resistion
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Re: Proof of 1z
resistion   2/11/2016 10:20:41 AM
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32 seems most realistic. But the die photo showed 15% of the die area outside the array. I wonder with double the layers, how much extra area there is outside the array.

rick merritt
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Re: Proof of 1z
rick merritt   2/9/2016 9:12:36 PM
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Micron PR would only say that "at this time we are not disclosing the number of tiers for the next generation of our 3D NAND."

Eli Harari guessed it was 32 layers.

rick merritt
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Re: Calling V-NAND users
rick merritt   2/9/2016 5:55:12 PM
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@GSMD  Holler when you hit a major milestone on this open SSD design

resistion
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Re: Proof of 1z
resistion   2/9/2016 5:47:19 AM
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The one at IEDM 2015 was 32 layers and 42100 nm2 repeated cell per layer.

http://www.chipworks.com/about-chipworks/overview/blog/intelmicron-detail-their-3d-nand-iedm

They had some room to shrink and were also planning to stack. But shrinking does seem very nontrivial, considering the extra floating gate thickness.

 

GSMD
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Re: Proof of 1z
GSMD   2/7/2016 10:10:14 PM
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On behalf of all the EE Times readers we can file a class action suit to force Micron to reveal all the details. The grounds being mental agony caused! Seriously, I checked with Micron and am yet to get the details. It us not as if the layer count is a state secret.

resistion
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Re: Proof of 1z
resistion   2/7/2016 9:54:34 PM
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If it is 32 layers, then the channel width should go up quite substantially, maybe >10 nm. The etched hole could be >70 nm but you'd have substract the thicknesses of the ONO, floating gate and tunnel oxide.

GSMD
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Re: Proof of 1z
GSMD   2/7/2016 9:14:40 PM
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Or have they increased the layers to 48 or maybe 64 ? Still requires a geometry shrink but not a dramatic one. Write speeds are down, so some shrink has happened. Drives researchers crazy when details are hidden.

resistion
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No 3D commitment?
resistion   2/7/2016 7:55:18 PM
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Executives at Micron have not yet decided whether they will commit to manufacturing the design as a product, Tomoharu Tanaka, a Micron fellow and author of the paper told EE Times.

The comment from Mr. Tanaka is that there is no executive commitment to making 3D NAND a product? It suggests the 3D floating gate processing is still too expensive?

GSMD
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Re: Calling V-NAND users
GSMD   2/7/2016 6:35:06 PM
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Well aware of Diablo. SSD controllers are one of the last bastions of closed systems, so we figured we will do our own open source open source ssd and nvdimm controllers. Try getting permission to develop open source firmware on any ssd controller and you will understand our motivation ! We also needed to develop a controller for our lightstor storage system that we are developing along with the folks at the IT Univ. Of Copenhagen. This is designed to be backward compatible with NVMe and supports features like compute in storage. CPU cores in the ssd controllers can be ARM or our own SHAKTI cores. Most likely the pcb design will also be open source. The idea is that you buy a bare bones ssd card and populate it with your choice of slc, mlc, tlc or nvram modules. Theere is naturally resistance to such commoditization ! It is in this context that we wanted larger geometry flash, low levels of write disturbance makes error correction easier.

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