Camera provides 3D vision
SAN FRANCISCO – This 19-image sampler of innovations and innovators at the International Solid-State Circuits Conference (ISSCC) captures only a slice of the 200 sessions attended by nearly 3,000 engineers here. They showed a cornucopia of products spanning everything from automotive electronics to ultra-fast NRZ wired interconnects.
All images by EE Times
We start with Dongsuk Jeon of Seoul National University (above) who started work on a portable assistant for the visually impaired while at MIT. It uses LEDs and a time of flight sensor (below) to map out the immediate area currently on an FPGA. Results are reported over Bluetooth to a handheld Braille device that indicates safe directions to walk.
The device is currently packaged in what looks like a camera case. Jeon plans a version that could fit inside a pendant or equivalent of a small flashlight.
Next page: More accurate, secure fingerprint recognizer
More accurate, secure fingerprint recognizer
Hao-Yen Tang (below), a graduate student at UC Berkeley, attracted the attention of Invensense with his idea for an integrated ultrasonic fingerprint sensor. Unlike today’s capacitive devices it is not fooled by humidity or spoofing.
The sensor notices the impedance mismatch for signals from direct skin contact versus ones passing through air gaps in epidermis valleys and sweat pores. It uses a 43x58 MEMS pixel array bonded to a CMOS processor to deliver images at a 500 dpi resolution.
Tang is already working part time at Invensense to help bring the component to market.
Next page: Turning up the volume
Turning up the volume
Thomas Hansen (below), of Merus Audio, a ten-person startup in Denmark, showed a 2x70W five-level Class D audio amplifier suitable for powering bookshelf speakers. The device uses less external filters to help cut board space by as much as 60% over existing parts while delivering a longer battery life.
Next page: Silicon drives small cells
Silicon drives small cells
Nicholas Klemmer (above), of Texas Instruments, shows a demo board running his two-chip base station. The integrated 45nm DSP and 2x2 MIMO RF chip support 200 MHz channels. That’s an order of magnitude wider than some base stations today, increasing capacity for carriers trying to serve urban users.
TI already has two large base station OEMs planning to use the chip. While the DSP board (below) is small, it also is very dense, packed with external clocking, power management and board-control ICs.
Next page: Wi-Fi targets the Internet of Things
Wi-Fi targets the Internet of Things
Ao Ba (below) showed one of the first transmitters for the emerging 802.11ah standard aka HaLow for running Wi-Fi over sub GHz bands. The chip is a collaborative effort between the Holst Centre in the Netherlands and the Imec research institute in Belgium.
The chip uses a polar architecture to trim maximum power consumption to 7.1mW while delivering data at rates of up to 5.7 Mbits/s. The resulting 1.3nJ/bit efficiency represents a ten-fold power reduction compared to state-of-the-art OFDM transmitters, the group claimed. The low power and high throughput are geared for the kinds of IoT nodes the 11.ah standard targets.
Since the paper was submitted, the team finished work on the receiver.
Next page: Kandou plants seed in multi-chip module
Kandou plants seed in multi-chip module
Startup Kandou Bus has a novel technique for packing more bits down a wire. Getting the world to adopt a new communications coding scheme is not easy, although the company is gaining traction at Jedec and the Optical Internetworking Forum.
While those efforts percolate, Kandou engineers implemented a way to use its technology to speed up connections between die in a multi-chip module (below). The approach packs 20.83 Gbits/s/wire across 12mm for an efficiency rating of 0.94 pJ/bit.
At least one big company is said to be adopting the approach in a product that could ship next year. Perhaps that’s what’s putting a smile on the faces of Kandou engineers Chrisoph Walter and Anant Singh (above).
Next page: KAIST sharpens view of augmented reality
KAIST sharpens view of augmented reality
Researchers such as Seongwook Park (above) of Korea’s KAIST research institute showed their third generation augmented reality glasses at ISSCC. The latest version can show a virtual keyboard to let users type anywhere. Its processor (below) supports gesture recognition and learning algorithms so over time it could even help you increase your typing rate.
Next page: MIT shows efficient AI accelerator
MIT shows efficient AI accelerator
Yu-Hsin Chen (below, right) of MIT explains his Eyeriss accelerator at an ISSCC demo session. The 65nm chip got results that compared to those from a 28nm Nvidia Tegra while being ten times more power efficient, Chen claimed.
He demoed the chip using AlexNet which has popularized convolutional neural networks now being widely used in data centers for a variety of jobs including image recognition.
Chen’s chip used a data flow approach, distributing control and storage to a 14 x 12 array of processing elements connected to an on-chip network using both point-to-point and multicast techniques. “Moving data is expensive so three types of data reuse are employed in the array,” Chen said.
Next page: Panasonic sees better than your eye
Panasonic sees better than your eye
The demo of Panasonic’s photoconductive image sensor was so secretive that the entire board was covered in black cloth. Engineers still almost refused to let me take a picture of the displayed results.
A version (above) with three-micron pixels was shown detecting images on fan blades that could not be seen with the human eye. Another version (below) used six-micron pixels and showed greater color saturation under difficult lighting conditions than today’s CMOS imagers.
So far, the work is only a research project seeking applications, said a Panasonic engineer.
Next page: Renesas steers video processor to cars
Renesas steers video processor to cars
As noted elsewhere, Renesas stole the show at the processor session with two high-end automotive chips including a video processor it demonstrated running both multiple streams of entertainment videos (above) as well as dashboard graphics (below).
Next page: FPGAs, ASICs burn up the wires
FPGAs, ASICs burn up the wires
Xilinx demonstrated a next-generation Ultrascale+ FPGA made in a 16nm finFET process running 64 Gbit/s signals using non-return-to-zero modulation. At this level and without such muscular silicon, many engineers are seriously considering the switch to more complex PAM-4 modulation.
Just across the way Socionext, the ASIC design company formed by Fujitsu and Panasonic, showed a similar capability with a 28nm device running 56 Gbit/s data while consuming 247 mW.
Next page: NXP hosts a car talk
NXP hosts a car talk
Attendees gathered around an automotive demo based on a keynote from NXP.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times