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TSMC Details Silicon Road Map

FinFETs will fly from 16nm to 7nm
3/16/2016 06:30 AM EDT
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rick merritt
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Re: Economics of FPGAs
rick merritt   3/20/2016 9:15:49 AM
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@ Mike@FH  Well the Xilinx chips are 16nm ones, not $10 so somewhat less expensive.

But ths idea of one design with many SKUs enabled with blown fuese at the factory or with firmware upgrades in the field is an increasingly popular concept. The GSA promoted it recently in an article here:

Chip Makers Need New Business Models

Mike@FH
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Economics of FPGAs
Mike@FH   3/19/2016 4:06:46 PM
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If it really takes $150m to produce a 10nm IC, and I think this is roughly accurate, I cannot see how Xilinx can do 'multiple chips' with revenues of only $2.5bn. 

Surely they just design one part and have ways of disabling parts of the die for smaller devices ?

resistion
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Re: ....
resistion   3/19/2016 4:05:18 AM
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Furthermore, Intel 10nm taken to be 55 nm gate pitch and 38 nm metal pitch. https://www.semiwiki.com/forum/content/5019-xilinx-skips-10nm.html So the process for their 10nm can be reused for 7nm.

resistion
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Re: ....
resistion   3/17/2016 7:41:14 PM
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Sounds about right, +/- few nm. But a few nm could mean a lot more now.

resistion
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Re: Reducing Cuts
resistion   3/17/2016 7:38:26 PM
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EUV doesn't have 2D flexibility (including cuts) at 7nm, so it has no advantage in the end. Three 193i masks still preferred to one 193i + one EUV especially only intended on limited layers anyway.

rick merritt
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Re: Reducing Cuts
rick merritt   3/17/2016 5:54:02 PM
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@resistion Are you saying SAQP at 7nm is more cost effective than EUV?

rick merritt
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Re: ....
rick merritt   3/17/2016 5:51:33 PM
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@realjjj Thanks for these details:

"On 10nm i think TSMC has gate pitch at 70nm and metal pitch of 46nm while Intel on 14nm is at 70 and 52nm."

Do others think these numberds are accurate?

Gondalf
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Re: Altera update
Gondalf   3/17/2016 5:11:17 PM
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I wonder what was the issue here. I have the feeling this is only the last attempt to make a really profitable 14nm FPGA; this is not the first 14nm tape out from Altera but one of a long serie. 

IMO 14nm FPGAs ended all too expensive to commercialize, after all this Intel node is very compact vs. TSMC 16nm and the defectiveness was pretty high on large dies for a long time.

I have the suspect Xilinx skipped TSMC 10nm only to avoid the same problems, delaying the shrink on a finer node. We are not sure Xilinx will not face the same yields wall at 7nm, if it will happen Xilinx will be costrained to stay on 16nm for a long time.

Time will tell, one thing is pretty certain: in these days all companies is bullishing a lot. 

resistion
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Reducing Cuts
resistion   3/17/2016 8:27:29 AM
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There is a famous slide by Intel showing four colored cuts. It's a marketing for use of EUV single cut. But actually now, multiple adjacent cuts can be replaced by one cut, one block. The block separates the cuts, effectively.

So as a result SAQP/LE2 (193i) should be doable and is definitely preferred to SAQP/EUV. Actually EUV may need to be LE2 already for the cuts at 7nm (sub-30 nm pitch).

ScottenJ
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Re: aggressive 7nm
ScottenJ   3/17/2016 12:14:35 AM
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Agreed but TSMC makes logic.

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