SAN JOSE, Calif.—Taiwan Semiconductor Manufacturing Co. Ltd. is ramping its 16nm process and making progress on plans to roll out 10 and 7nm nodes over the next two years. The news injected optimism in a crowd of about 1,500 attendees at a Silicon Valley event here where the world’s largest independent chip foundry shared its long-sought success with FinFETs and the great unknown beyond.
Some observers were underwhelmed, claiming TSMC’s road map to 7nm will only bring it in line with the 14nm process in which Intel is currently ramping its Skylake CPUs.
Indeed, even TSMC executives noted its 10 and 7nm nodes will have minimum feature sizes of about 20 and 14nm, respectively. And they all use the same fundamental FinFET transistor structures Intel pioneered at 22nm and 14nm. However, they also reported significant progress on research on post-FinFET devices.
At the event, TSMC provided a wealth of details about its current and future nodes, but said little about cost. Analyst Handel Jones of International Business Strategies (Los Gatos, Calif.) estimates it could cost as much as $150 million to make a 10nm chip, a data point TSMC execs quoted but didn’t confirm.
Customers such as Xilinx skipped TSMC’s first generation 16nm FinFET process. But Xilinx chief executive Moshe Garielov was effusive about the 16FF+ process in which he is now building multiple chips, claiming a lead over rival Altera which he said is waiting to tape out 14nm chips in the fabs of its new owner, Intel.
One of the new Xilinx 16nm FPGAs packs 5.2 billion transistors to support seven programmable cores. “We have the only [16nm FPGA] out and we believe we have a year advantage,” he said.
Analyst Jones claimed in January only a handful of 16nm chips were in volume production even though the original process had been in the works for some time.
TSMC execs declined to comment except to note the foundry started volume production of 16FF+ in the third quarter of last year. It had 50 16nm tape outs last year and expects another 70 this year, ramping to capacity of 300,000 16nm wafers/quarter by the end of the year. Most of the ramp will come between June and October.
The foundry also is ramping a low-power version, 16FF Compact (16FFC) that supports operating voltages down to 0.5V for mid- and low-end smartphones, wearables and the Internet of Things. It will be ready for volume production by April.
Third parties including ARM, Dolphin, Imagination Technologies and Synopsys will roll out IP reference subsystems for the process late this year. Some blocks such as embedded flash, Bluetooth and Zigbee transceivers and embedded power management blocks are not yet ready, said Cliff Hou, vice president of R&D for design platforms at TSMC.
Car makers will get their own variant of the 16nm process that should be ready to make ADAS and infotainment chips by mid-2017. IP blocks for the process will be certified for ISO26262 and AEC-Q100 Grade 1 standards important for car makers. TSMC has supported automotive-specific variants since the 90nm node.
Next page: Progress at the 7nm node
A fab worker inspects a 12-inch wafer. (All images: TSMC)