TSMC Details Silicon Road Map

Mark Liu, TSMC’s co-chief executive officer, reported at 7nm the company has 30% yields of a fully functional 128 Mbit SRAM. The process will deliver either 15-20% more speed or require 35-40% less power and deliver 1.63 times the logic density compared to chips made in its 10nm process, he said. It will be available for what TSMC calls “risk production” about a year from now.

At 7nm, the foundry will support different variants of the node for mobile, high performance computing (HPC), IoT and automotive chips. The move marks the most differentiation the foundry has ever attempted with a single process, reflecting the increasing diversity of semiconductor requirements.

“Over the last few years mobile was the major driver, so we put a comprehensive ecosystem for mobile in place,” said TSMC’s Hou. “Looking forward, it’s not only about mobile but HPC, automotive and IoT, and their design needs are very different,” he said.

The 7nm platforms will have their own development kits, EDA tools and IP blocks. In addition, companies such as ARM and Imagination Technologies will provide IP reference subsystems and optimized processors to speed SoC integration and verification, said Hou.

The HPC variant will make chips that run 10-15% faster than those made in the mobile process, enabling clock trees optimized to hit 4 GHz data rates. The variant will include optimized SRAM compilers supporting L3 caches and taller standard cell libraries. Early versions of the tools and IP blocks will be available later this year.

TSMC will enable silicon interposers larger than 1,200mm² — 1.5x the reticle size — at 7nm to enable giant 2.5-D stacks of logic and memory for the next generation of what it calls Cowos (chip on wafer on substrate). The foundry taped out last month a 16FF+ device merging a CPU and two HBM2 memory stacks on a silicon interposer to pave the way for its 7nm offering.

The prototype will complete silicon validation this fall. The expanded 2.5-D packaging capability could be available at 7nm in 2018. Near term, versions of the process could support a 16 or 10nm processor or ASIC with up to four HBM2 stacks.

The good thing about the 7nm node is it uses about 90% of the same tools as TSMC’s planned 10nm process, including existing 193nm lithography steppers. The bad news is it requires as many as four resolution enhancement techniques and self-aligned quad patterning with some dimensions as small as “4nm and below for precision cuts at less than 30nm pitch,” said Y.J. Mii, a vice president of R&D at TSMC.

For dimensions where pitch is smaller than 20nm, TSMC will need to use direct self-assembly. DSA’s “chief challenge is its defect density is now five defects per wafer per pass, but its improving,” said Mii.

TSMC recently said it is testing extreme ultraviolet lithography at 7nm for production use at 5nm. “We invest significant effort in EUV for 7nm and beyond,” said Mii.

A single EUV exposure could eliminate three extra masks needed with 193nm steppers, and 2-D layouts in EUV show better corner rounding and line shape. “With this capability, we can enable more flexible design and reduce process complexity,” he said.

Most EDA design rules and layout styles for 7nm are complete but circuit design tools and IP blocks are still in the works, said Hou. TSMC’s Integrated Fan Out (InFO) flip-chip packaging capability should be available for 7nm by June 2017, about a quarter after first “risk” tape outs begin.

TSMC had surprisingly little to say about its 10nm node and how it differs from today’s 16FF+ process. It did claim the process will be denser than that of rivals. It started early tape outs this year for some customers though volume production is not expected until next year.

After the delays getting 16nm off the ground, attendees might feel skeptical the foundry will start to ramp 10 and 7nm processes over the next two years. However the challenges commercializing FinFET transistors were greater than the relatively straightforward shrinks at 10 and 7nm. Unfortunately their benefits are also likely to be less great, probably a reason why TSMC did not make comparisons between 16 and 10nm nodes.

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