REGISTER | LOGIN
Breaking News
News & Analysis

Silicon Lacks Clear Metrics

No one number pegs a process
3/24/2016 11:08 AM EDT
17 comments
Page 1 / 2 Next >
More Related Links
View Comments: Newest First | Oldest First | Threaded View
Page 1 / 2   >   >>
Gondalf
User Rank
Author
Re: TSMC metal pitch shrink
Gondalf   8/18/2016 4:51:50 AM
NO RATINGS
The numbers floating around the web about TSMC 10nm say:

0.70 nm Contacted Gate Pitch (x0.78)

0.46 nm Interconnect Pitch (M1) (x0.72)

I don't see a full node ahead Intel 14nm, the two processes are neck to neck with a small advantage for TSMC but nothing of dramatic that could change the performance of a SOC in a relevant manner. So apparently Intel is right saying that upcoming TSMC 10nm is a copy of present Intel 14nm. 

Obviously we must to see if real products from TSMC will sport these geometry values or they will are more relaxed to allow better yields and the correct heat dissipation.

Marketing !!!!

ps. Samsung 10nm will be more compact than TSMC, a little less than an half node ahead Intel 14nm. 

64nm Contacted Gate Pitch  (official value)

48nm Interconnect Pitch Pitch (M1) (official value)

I repeat that for sure these are best case values and working silicon is likely a lot more relaxed in sram cells....like it happens in Intel cpus.

IMO these numbers do not gives an idea of the real silicon shrink of a process shift because manufacturers relax the compactness to avoid the incredible power density of these fine FinFet nodes unable to dissipate heat correctly like a planar process does.

 

 

 

 

 

resistion
User Rank
Author
TSMC metal pitch shrink
resistion   8/18/2016 1:02:55 AM
NO RATINGS
"That said, TSMC has achieved metal-layer 1 pitches at 10nm that are "a full shrink (~70%) ahead of Intel's 14nm"


So TSMC is at ~36 (~0.7*52) nm metal pitch for 10nm node?

Roger3
User Rank
Author
Re: Your metric?
Roger3   3/29/2016 7:00:00 AM
NO RATINGS
Rick,

Excellent article, congratulations ! We cannot imagine how many decisions were made based on such misleading coding scheme !  My suggestion is basically give each process a sequence code , like X1, X2 , X3 , etc. Each one will have its specs, as it was in the past.  If the foundries don´t make it , EETIMES could !

 

chipmonk0
User Rank
Author
Re: Your metric?
chipmonk0   3/28/2016 4:56:46 PM
NO RATINGS
at every smaller / new node these Foundries just build Test Chips with SRAM ( pretty generic design ) and peddle their metrics ( speed, power, density,  .. , pricing, schedule,.. that sort of thing ) to their Fabless customers to benchmark against other suppliers.

hjones0
User Rank
Author
Product competitiveness
hjones0   3/25/2016 4:41:56 PM
NO RATINGS
3D structures are much to complex to be compared with a few simple metrics

There are tradeoffs between power and performance that need to be taken into account as well as transistor density metrics

Interconnect delays which include the vias metal and dielectric structures and first level off chip interconnect can have 5X the impact on performance than differences in the gate stack

Parametric and systemic yields need to be key metrics for the manufacturability of the technology which can give transistor costs

Bit cell characteristics need to be measured as a part of a design

What is needed is an industry standard test chip that has processors SRAMs and I/O structures that can be mearured within a range of operating environments

Hope the wafer manufacturers accept this concept

 

 

realjjj
User Rank
CEO
Re: Your metric?
realjjj   3/25/2016 3:51:51 PM
NO RATINGS
I think Samsung's HP cell is 0.080, 0.064 being HD. That could explain the SRAM discrepancy.

 

DataMuncher
User Rank
Author
Re: Your metric?
DataMuncher   3/25/2016 2:35:17 PM
NO RATINGS
A few good examples of challenges and opportunities using geometry metrics can be found in Bill Holt's Intel Investor Pitch from Nov 15.  It compares transitor density for Apple A8 (20nm TSMC) and A9 (14nm Samsung and 16nm TSMC) against roughly comparably-sized Intel Broadwell and Skylake dies (14nm High Perf P1272) 

* Intel 14nm has far smaller feature sizes, and M1*G pitch products than either TSMC or Samsung, but a lower raw transistor density than even TSMC 20nm when these different designs are compared.

* But as Intel explains, they use a different composition of foundational IP in their CPUs, vs. Apple SoCs so the raw transistor count really needs to be normalized based on size of the transistors and the % composition of each these different types of IP building blocks. I'm a bit skeptical about the whole somewhat arbitrary normalization process.

* But the the TSMC A9 vs. Samsung A9 comparison is intriguing since it is an (no pun intended) apples-to-apples matchup.  Both were design to have exactly the same performance and power characteristics using presumably similar methodology and libraries (track sizes), and we see a relatively small difference in transistor density.  The slightly tighter density of the Samsung version seems to correlate with the tighter gate pitch and legnth, though the larger % of the Samsung design committed to SRAM, doesn't correlate with the smaller Samsung bit-cell size.

See foils 18-20

http://files.shareholder.com/downloads/INTC/0x0x862743/F8C3E42B-7DA9-4611-BB51-90BED3AA34CD/2015_InvestorMeeting_Bill_Holt_WEB2.pdf

realjjj
User Rank
CEO
Re: analyst
realjjj   3/25/2016 12:24:17 PM
NO RATINGS
Is there real competition between Intel and TSMC in the foundry space? Can it be if Intel doesn't spin-off  the foundry to work closer with the ecosystem? If they would do that ,maybe they can compete at 5nm in 2020 but can they really compete otherwise?

And what's after 5nm if they stay on course? The PC market could be at 150-165 million units by 2020 ,assuming 280 million units in 2015 - 5% drop this year (likely more), 8 % in 2017 and 15% in the next years due to foldable screens in mobile. ASP erosion and increasing pressure from AMD would make it worse for Intel in PC while in server AMD and ARM might take some share. If there is no breakthrough in 3D logic or beyond to enable Intel to win in glasses , will they have the resources to keep going or will they drag the foundry down with them? More than 100% of their op income is from PC and server today.

Sure TSMC, Samsung , GloFo make it easier for others to take on Intel in server and for AMD to take share in PC.

hjones0
User Rank
Author
Re: analyst
hjones0   3/25/2016 11:36:34 AM
NO RATINGS
Rick Wanted to clarify that Intel 10nm and TSMC 7nm are close from a  physical dimension perspective

Intel 10nm is planned for mass production H2 2017 and TSMC 7nm ( HPC and M ) in mid 2018

A key issue is what designers can do with the process. which includes libraries,foundation IP,complex IP,bit cells ,memory compilers, wafer scale packaging etc

It is good for the electronics industry that there is intense competition between Intel and TSMC

It is also good for the tooling vendors because the have a larger customer base for their advanced equipment

It is good for Sunit to be back in action and his intellect is missed

DataMuncher
User Rank
Author
Re: Your metric?
DataMuncher   3/25/2016 2:51:41 AM
NO RATINGS
GF and Samsung also do some process validation on ARM cores, though not always the same ones, and nowhere near as comprehensively and consistently as TSMC from the data I have seen. Intel Custom Foundry seems to be using Imagination GPUs instead. But none of it is apples-to-apples on the same cores, so yes, it is hard to shop around without doing your own detailed multi-process comparison. The other big variables are true timelines / yield learning and interface/analog IP availability for a given set of processes.

Page 1 / 2   >   >>
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed