SAN JOSE, Calif. – The semiconductor road map is shifting as advances in semiconductor technology become harder and market drivers become more diverse. That’s the message from this year’s VLSI Symposia, an annual gathering of top chip technologists that released its program this week.
More than 220 papers at the event will describe innovations to drive process technology to 10nm and beyond. Another 350 will describe circuits that squeeze power consumption for use in the Internet of Things, automotive electronics and big data analytics.
The event’s plenary sessions make clear the times are changing.
A panel of experts from companies such as Intel, IBM and Globalfoundries will discuss the implications of the slowdown in chip scaling in a session entitled “More Moore, More than Moore or Mo(o)re Slowly.” A separate panel will discuss “Semi Business beyond Scaling.”
“As we reach the limits of geometric scaling, we must add a critical functional scaling dimension to our technology innovation through 3D, embedded emerging memories [and] system-in-package,” said Raj Jammy, general chair of the Symposium on VLSI Technology, speaking in a press release.
Indeed, this week Intel, the world’s largest chip maker, quietly acknowledged in a quarterly earning report (see page 14) that it will continue its plan to stretch out the time between new process nodes. The company plans to release three generations of microprocessors at 10nm as well as 14nm, it said. In the past it made just two generations of chips in a process, rolling out a new node every two years.
“We expect to lengthen the amount of time we will utilize our 14nm and our next-generation 10nm process technologies, further optimizing our products and process technologies while meeting the yearly market cadence for product introductions,” Intel said.
Intel will stretch its 'Tick-Tock' two-year cadence for rolling out new process technologies to a three-year span at 14 and 10nm. (Source: Intel)
Microprocessors, once the primary driver for semiconductors, now share the road with a variety of automotive and IoT applications. Thus keynoters at the VLSI event include an engineering executive from Nissan discussing electric and self-driving cars. Speakers from Invensense, Qualcomm and Sony will provide perspectives on sensors, robotics and imagers, respectively.
The talks make clear a shift from days when the event focused on ever denser, faster computer chips. “The Internet of Things, big data and smart cars have put the center of gravity around heterogeneous integration, with RF, mixed signal, digital and packaging technologies in the first row,” said Jammy.
In the Circuits Symposium, Intel will describe two 14nm devices. An energy harvesting wireless sensor node for IoT using a 32-bit x86 microcontroller –presumably a version of Quark – will run at near‐threshold voltage. Among data center chips, it will detail a 2.1 GHz regular expression matching accelerator running at 350mV‐900mV.
New materials and gate structures will be the focus on many papers in the Technology Symposium. Samsung will give one of the first descriptions of its 10nm FinFET process, and IBM will talk about its work on a 10nm FinFET technology using a high mobility silicon germanium channel.
Several papers will discuss novel transistor designs targeted at the post-FinFET nodes of 5nm and beyond. TSMC will describe an indium arsenide gate-all-around nanowire with a 12-15nm diameter. Academics from KU Leuven in Belgium will claim record performance with an indium gallium arsenide nanowire.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times