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3/31/2016 10:48 AM EDT
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Re: Talking Open Source
DigitalEngineer   4/6/2016 2:55:50 PM
Thank you for your answer. What about fence and system instructions. Do you mind telling me, why they are missing ? Will they be implemented later. I'm not an expert in this subject. Thanks a lot in advance.


Francesco Conti
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Re: Talking Open Source
Francesco Conti   4/4/2016 9:08:40 AM
Hi DigitalEngineer,

I am a member of the PULP group as a researcher in both University of Bologna and ETH Zurich.

You are right that the tool chain and the multi-core platform have not been released in the open yet. However, we are working hard toward releasing both of them - we never intended PULPino to be the "final" step in open-sourcing the PULP platform, but merely the first step. Eventually, our plan is to release the whole platform, save of course for IPs that depend on private agreements between ETHand/or University of Bologna and other parties.

For several reasons our RISC-V toolchain could not be open-sourced together with PULPino. I cannot give a definite date, but we should be able to solve most problems related with it relatively soon, and then it will be open-sourced immediately.

For a public release of the multi-core platform (which is one of our main objectives - hence the name PULP that stands for Parallel Ultra-Low Power Platform), there will be need of a bit more time. We want this to be well polished and ready. However, parties interested in collaborating can already contact us privately (e.g. via the contacts on our website

Hope this solves some of your doubts!

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Talking Open Source
DigitalEngineer   4/1/2016 6:20:03 PM

I would be so happy (for the first time), if I'm wrong, but my understanding is:

The multicore version is not released.

The single core version is based on RI5CY. The RI5CY has some enhanced features, but you cannot use them, because no tool chain is released (or at least removed from github again, if I understand one of the Pulpino key guys correctly).

What is left (from the OPEN SOURCE perspective) is yet another RV32IM with some  feature overhead implemented which you cannot use, plus some standard SoC peripherals.

I applaud their work and would love to build my work on theirs. So please can someone tell me that I'm wrong (not for the first time) and point me to the appropriate open source files. Can't wait ...


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Also on FD-SOI
Adele.Hars   4/1/2016 12:46:38 PM
Peter, there's been significant work in 28nm FD-SOI on PULP, too -- see for a paper these guys did with ST in November. The authors note that their paper reports on, "...the first ever implementation of a 4-core cluster fabricated using conventional-well 28 nm UTBB FD-SOI technology. The multi-core architecture we present in this work is able to operate on a wide range of supply voltages starting from 0.44 V to 1.2 V. In addition, the architecture allows a wide range of body bias to be applied from −1.8 V to 0.9 V. The peak energy efficiency 60 GOPS/W is achieved at 0.5 V supply voltage and 0.5 V forward body bias. [...] Even when compared to other low-power processors with comparable performance, including those implemented in 28 nm technology, our platform provides 1.4× to 3.7× better energy efficiency." Parts Search

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