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Intel Plans A Future of CMOS

Moore's Law extended by new materials
4/5/2016 02:00 AM EDT
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R_Colin_Johnson
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Re: and... ?
R_Colin_Johnson   4/5/2016 6:58:12 PM
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Yes, turning on whole columns is good enough for now, but you are right they will have to go to sub-array architectures in the future. I'm still at the conference so I'l try to catch Zhang and ask him, if he hasn't already departed! Thanks for the comment.

finfet1
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and... ?
finfet1   4/5/2016 2:24:57 PM
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Interesting specifics especially on the SRAM sleep Vdd vs read Vdd, but at a fine granularity this wouldn't work, obviously.  The overhead in charging the power rails up and down at a high frequency for reading different rows would probably offset the power savings. 

So then it comes down to a tradeoff between granularity of sleep/active rail application -- do you apply to specific sections of rows?  Or to small sub-arrays ?  My guess is on small sub-arrays with some intelligent digital management that acts like a virtual address map that maps active addresses to arrays so that active addresses are kept densely in the same sub-arrays.

It also comes down to a tradeoff between VDD voltages -- obviously retention voltage is probably 15-20% above near-threshold, with the tradeoff being on the tolerances of the sense amps, which are probably also PVT dynamically adjustable and digitally tuneable.

 

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