TORONTO –- Rumors about the death of Moore's Law have been greatly exaggerated in recent years, and Samsung Electronics' mass production of what the company said is the industry's first 10nm 8Gb DDR4 DRAM chips shows DRAM scaling has yet to hit the proverbial wall.
In a news release, Samsung said its new DRAM supports a data transfer rate of 3,200 Mbits/second, which is more than 30% faster than the 2,400 Mbits/sec rate of 20nm DDR4 DRAM. The new modules produced from the 10nm-class DRAM chips consume 10% to 20% less power compared to their 20nm process-based equivalents, making them ideal for high performance computing systems as well as the PC and mainstream server market.
Samsung said it addressed DRAM scaling challenges using currently available argon fluoride immersion lithography without the use of extreme ultra violet equipment. The company began mass-producing 20nm 4Gb DDR3 DRAM in 2014, and said its 10nm class DRAM is in part the result of its process a step further.
Samsung created the new 10nm cell structure by using a proprietary circuit design technology and quadruple patterning lithography, which enables use of existing photolithography equipment. Use of a refined dielectric layer deposition technology enabled further performance improvements, which engineers applied with uniformity to a thickness of a single-digit angstrom, which is one 10 billionth of a meter, on cell capacitors, resulting in sufficient capacitance for higher cell performance.
Quadruple patterning lithography has been used for NAND flash for number of years, said Jim Handy, principal analyst with Objective Analysis in a telephone interview with EE Times. Double patterning has been sufficient for 20nm DRAM, but going below that requires quadruple patterning. What's most notable about Samsung's announcement, he said, is that it continues Moore's Law, which not long ago wasn't expected to continue below 20nm. However, it's not the only memory maker that anticipated this shrink as Micron had previously said it had clear visibility into three nodes beyond 20nm.
Samsung's 10-nm DRAM supports a data transfer rate of 3,200 Mbps.
In NAND flash memory, a single cell consists of only a transistor, whereas each DRAM cell requires a capacitor and a transistor that are linked together. According to Samsung, 10nm class DRAM presented another level of difficulty in that it had to stack very narrow cylinder-shaped capacitors that store large electric charges on top of a few dozen nanometer-wide transistors to create more than eight billion cells.
Handy said changing materials to a build a capacitor that small to hold enough of a charge was necessary, and there's been steady changes in DRAM dielectric material for some time now. “Everybody's going to have to do that," he said. “They've been moving in that direction since the late '90s, even before."
While Samsung said in its announcement that its new 10nm DRAM will accelerate DDR4 adoption, Handy said it is already moving along as anticipated.
“Any new DRAM that anyone introduces had better be DDR4 because DDR3 is on its way out," Handy said, noting that the continuation of Moore's Law means we're going to continue to get cheaper DRAM.
Samsung said it would offer a wide array of 10nm class DDR4 modules with capacities ranging from 4GB for notebook PCs to 128GB for enterprise servers, while extending its 20nm DRAM line-up with its new DRAM portfolio throughout the year. It will also be launching 10nm class mobile DRAM products with high densities in the near future to address the ultra-HD smartphone market.
—Gary Hilson is a general contributing editor with a focus on memory and flash technologies for EE Times.