SAN JOSE, Calif. — Google’s new processors for accelerating machine learning were built under a tight schedule, said Norm Jouppi, a veteran chip designer and distinguished hardware engineer who led the effort.
“I joined Google 2.5 years ago, and there were already some efforts underway…The emphasis was on getting something out quickly,” said Jouppi in an interview with EE Times.
A decision was made about three years ago to make a custom chip to accelerate Google’s machine learning algorithms. Jeff Dean, a top Google software engineer, helped drive the project in its early days.
The chips, called tensor processing units (TPUs) after the Google TensorFlow algorithm they accelerate, have been running for more than a year in Google’s data centers. “The sked was pretty challenging, the team did really well on that—a short schedule can help focus you, it answers a lot of questions,” Jouppi said.
Before Jouppi arrived in September 2013, Google engineers had evaluated using CPUs, GPUs and FPGAs. “They decided the benefits of customization were great enough that they wanted to go straight to custom silicon,” he said pointing to a paper from Mark Horowitz of Stanford suggesting custom silicon can deliver improvements of an order of magnitude
Google may reveal some details about the TPUs in the fall, but for now it is keeping mum on their inner workings. For example, Jouppi would not comment on whether they handle training of neural networks. He would only say they are more efficient than standard parts because they use “lower precision only using as many bits as needed.”
Google may reveal details about its TPU in the fall. (Image: Google)
Next Page: Calling your chip in the cloud