SANTA CLARA, Calif. – A handful of chips using PCI Express 4.0 are heading to the fab even though the 16G transfers/second specification won’t be final until early next year. Once it gets all the details sorted out, the PCI Special Interest Group (PCI SIG) aims to start work in earnest on a 5.0 follow on running at either 25 or 32GT/s.
Cadence, PLDA and Synopsys demoed PCIe 4.0 physical-layer, controller, switch and other IP blocks at the PCI SIG’s annual developer’s conference here. They showed working chips, boards and backplanes that included a 100 Gbit/s Infiniband switch chip using PCIe 4.0.
It’s been more than six years since the PCI SIG ratified its last major standard, the 8 GT/s PCIe 3.0. At the time it started the 4.0 version it thought it might be its last copper-based chip-to-chip interconnect. But since then Ethernet and Fiber Channel groups have pushed copper networking to 25 and 32 Gbits/s respectively.
“We know we can take PCIe to the next generation, we just have to work out the details,” said Al Yanes, president of the PCI SIG in a press conference at the group’s annual developer’s conference here.
Cadence showed a Mellanox 100G Infiniband switch chip (left) linked to its controller (on the red board, right) using PCIe 4.0 across a backplane (center). (Images: EE Times)
The questions about version 5.0 are many. They include determining if it will be backward compatible and still defined as a chip-to-chip link as all PCI standards have been to date.
“We can’t play the encoding trick,” said Yanes noting the version 3.0 adopted 128b/130b encoding up from 8b/10b previously used. “Using 256 coding won’t get you much more, so I don’t see many tricks besides increasing frequency” he added.
Demand will come from the usual suspects. Networking cards already hitting 100 Gbit/s rates will need faster chip links as will next-generation graphics processors and solid-state drives.
It’s not easy creating a standard used in everything from smartphones to supercomputers for a member base of 732 companies. As data rates increased and signal margins narrowed, the time between new PCIe versions lengthened from three to seven years so far.
Next page: Getting PCIe 4.0 out the door
Mellanox's switch is among a handful of chips about to tape out with PCIe 4.0.