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PCIe 4.0 Heads to Fab, 5.0 to Lab

Next-gen debate--25 or 32 Gbits/s?
6/28/2016 06:20 PM EDT
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rick merritt
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On the horizon
rick merritt   6/29/2016 1:02:17 PM
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Pete's comment below made me think about the comment of a Cadence rep yesterday who said he wants to keep fueling the PCIe engine because he sees new initiatives coming up that will require time and energy and provide new opportunities like the CCIX FPGA-to-accelerator interface.

What do others think about PCIe in regards to CCIX and other new initiatives?

For more on CCIX see http://www.eetimes.com/document.asp?doc_id=1329734

 

pete220
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PCIe Fan
pete220   6/29/2016 12:37:54 PM
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I've been using PCI and PCIe for a lot of years to connect FPGAs to CPUs for instrumentation.  I have never found anything as friendly as PCIe for that purpose.  The low latency memory mapped programming model is easy to use under Linux and RTOS.  The latest Xilinx Ultrascale FPGAs even have a special reconfiguration port built right into the PCIe hard core.  I look forward to using that.

This latest doubling of PCIe speed seems a little over the top but I suppose there are applications for it.  What a successful standard!

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