LAKE WALES. Fla—On the 20th anniversary of its invention at IBM Research, fabled nonvolatile "universal" magnetic random access memory (MRAM) is getting an upgrade. IBM announced today (July 7) that, in collaboration with foundry-giant Samsung, it is using a spin-transfer torque (STT) design on its MRAM.
Faster than flash and as dense as dynamic random access memory (DRAM), this universal memory genre is now being readied for manufacturing with a final round of material optimization and engineering finesse at IBM (Yorktown Heights, N.Y.). IBM says its STT MRAM access clocks at 10 nanoseconds and ultra-low-power (7.5 microamps), claiming its MRAM outperforms flash at the speed of DRAM. Applications include everything from tiny Internet of Things (IoT) system-on-chips (SoCs) to vast mass storage systems for servers.
20 years in the making
"IBM has been working for 20 years on the magnetic random access memory, or MRAM, starting from a DARPA [Defense Advanced Research Project Agency] funded research project, along with Motorola, on field-switched MRAM," Daniel Worledge, lead researcher, distinguished research staff member and senior manager of MRAM at IBM Research (Yorktown Heights, N.Y.) told EE Times. "IBM's John Slonczewski invented the spin-torque switching method for MRAM back in 1996, but at first we thought the field-switched method was best."
"We switched to the spin torque technique after a DARPA-funded research project with Motorola. Now we are celebrating its 20th anniversary after having scaled down the design to 11-nanometer in collaboration with Samsung," said Worledge.
Worledge does not believe that IBM's STT MRAM will replace DRAM anytime soon but believes it can replace embedded flash, since SST MRAM is easier to embed, faster and has unlimited reads and writes, unlike flash which is typically limited to 10,000. Next IBM plans to optimize the cell's engineering parameters, for mass production with a partner in as little as three years.
Each bit-cell of a spin transfer torque (STT) magnetic random access memory (MRAM) contains one transistor and one tunnel junction arranged vertically. The tunnel junction is composed of a fixed magnet whose north pole always points up, and a free magnet whose north pole points up or down depending on whether it is storing a '0' or '1', respectively. It is programmed by merely passing a 7.5 microamp current through it in the direction of desired polarization.
A transmission electron microscope (TEM) image of a single 11-nanometer junction of IBM's spin-transfer torque (STT) magnetic random access memory (MRAM).
The biggest challenge that the IBM/Samsung overcame was building a vertically oriented cell.
"We knew back in 2009 that to scale as well or better than DRAM we had to have a vertical magnetic cell, just as DRAM has to have a vertical capacitive cell," Worledge told EE Times. "But it took our earlier collaboration with TDK to create the vertical architecture. We also partnered with Micron briefly, which continues to work on MRAM, but it took our partnership with Samsung, which had its MRAM Forum at out Zurich Lab last week, to scale the vertical architecture down to 11-nanometers with a clear path to 10-nanometers."
The reason spin-transfer-torque is such an important part of the architecture, compared with the magnetic-field switched MRAMs being sold by EverSpin and others today, is that only 7.5 microamps is required to write a bit, compared to milliamps for field-switched bit-cells.
How it works
In more detail, IBM uses a single field-effect transistor (FET) controlling the read/write current flowing through a vertical magnetic-tunnel-junction (MRJ) in its STT MRAM. The FET, on the bottom of the stack, connects to the MTJ, which consists of a cobalt-iron-boron (CoFeB) layer with a fixed spin-orientation, a magnesium-oxide (MgO) tunnel barrier and a top layer of CoFeB whose spin can be changed thus storing the one or zero. The stack was capped with another MgO layer to enhance the perpendicular magnetic anisotropy (PMA) and reduce the spin-current loss related to spin-pumping.
Daniel Worledge, the lead research scientist and senior manager in the MRAM group at IBM Research, Yorktown Heights, N.Y.
The resulting bit-cell switches in as little as 10-nanoseconds by merely reversing the current through it. If the current flows up through the junction the bit is flipped to the same orientation as the bottom CoFeB layer. If current flows from the top to the bottom of the cell, the bit reflects backwards thus flipping the top CoFeB layer to the opposite spin relative to the fixed bottom CoFeB layer. Because no atoms are moved, this operation can be performed any number of times without limit. And by optimizing the engineering of the cell, its retention lifetime can be adjusted from 10-to-20 years, according to Worledge.
IBM scientist Janusz Nowak co-authored the IEEE Magnetic Letters paper on scaling the spin-transfer torque (STT) magnetic random access memory (MRAM) down to 11-nanometers.
"The key advantages of STT MRAMs are the combination of nonvolatility and infinite endurance unlike any other memory today or in the foreseeable future, plus its ability to have their retention adjusted by optimizing the size of the bits and the perpendicular anisotropy of the magnetic material," Worledge told EE Times.
In testing its design, the write-error-rate was one error in 1.4 billion writes, low enough to be easily made flawless with standard error-correction techniques, according to Worledge.
IBM scientist Guohan Hu holds a stack of spin-transfer torque (STT) magnetic random access memory (MRAM) wafers.
Get all the details in the paper titled "Voltage and size dependence on write-error-rates in STT MRAM down to 11 nm junction size" in IEEE Magnetic Letters.
— R. Colin Johnson, Advanced Technology Editor, EE Times
Article updated 7/7/16, 12:40PM Pacific: We changed the number of writes in penultimate paragraph to 1.4 billion from 70 billion writes at the request of IBM. The 70 billion is a correct number but may be misleading as it refers to longer test times at higher voltage, as detailed in IEEE Magnetic Letters. --EE Times
Good points. I think IBM meant in order to measure the write-error-rate they had to read the bits too, so proved it as a matter of course. Not sure what the read current was, but I believe production models will use higher currents than their test cases--this research was to see how low they could go and still maintain reliability.
IBM must have thought I was referring to write bit error rate. I was referring to disturb or read bit error rate. In other words, read current cannot be too close to write current. 7.5 uA write current is already small.
Yes, that would be a interesting graphic, since most of IBM's new technologies are experimental--such as nanotube and graphene transistors. This one, however, already has a foundry partner and a three year countdown. Yes, IBM has one of the world's thickest portfolios of patented semiconductor technologies--not all of which make it to manufacturing--but spin-transfer torque MRAM is all but a sure thing, with Micron, Toshiba and many others prepariing similar "universal" memory technologies.
Appears to be more IBM innovation vaporware. I applaud their spirit, but wish they would make announcements when they actually had a product ready for the market. I echo AKH0's comments.
It would be intriguing to research and prepare a table listing each of the IBM technology innovations announced on EETIMES over the past 20 years (about 2-4+ per year?), and then identify the product (if one ever was made) which used the actual technology.
IBM says you are wrong about this point too, because advanced sense amp designs do allow sensing at these low currents. Whether you would go as low as 7.5uA for the write current in a production model is debatable, according to IBM, but it says the point is that the device physics still work at these dimensions and low currents, with reliable writing all the way down to as low as you could possibly want the write current to be.
Yes the thermal stability needs to be improved, as mentioned as of its goals in the paper, but their point was that this is the first time it was possible to achieve both low write error rate at low current, for any value of thermal stability.
The read-error-rate is at least as good as 7e-10, as stated in the paper, since otherwise read errors would have affected the write-error-rate measurement. In general, read-error-rate is not the limiting problem with MRAM, but write-error-rate is. Good read-error-rates were demonstrated many years ago, according to IBM. However, good write-error-rates at these low currents have never been demonstrated before, according to IBM.
In its paper IBM did not suggest stacking it in 3D, but they did say in the paper that its thermal stability is too low and needs to be improve. However, IBM says the point is that this is the first time it was possible to achieve such a low write-error-rate at such a low current, for any value of thermal stability.