TORONTO – Rambus Inc. said it has developed the first production-ready 3200 Mbps DDR4 PHY available on Globalfoundries Inc.'s FX-14 ASIC platform using its power-performance optimized 14nm LPP process.
The Rambus R+ DDR4 PHY intellectual property uses Rambus' proprietary R+ architecure, based on the DDR industry standard. The PHY is part of the Rambus' suite of memory and SerDes interface offerings for networking and data center applications, said Frank Ferro, senior director of product management at Rambus. Meeting the performance and capacity demands of those segments are a heavy focus for the company, he said in a telephone interview with EE Times.
While the high performance computing segment might be what comes to mind first, Ferro said Rambus is really looking to meet the needs of the Facebooks and Instagrams of the world as their data center requirements trickle down to the chip companies.
The new product follows two recent acquisitions by Rambus that Ferro said contribute to the company's overall goal of improving the interface between memory and the CPU. At the end of June, it announced its intention to acquire Inphi Corp.'s memory interconnect businessfor $90 million in cash to strengthen its position in the memory buffer chip market.
Earlier that month, Rambus announced it would acquire Semtech Corp.'s Snowbush serial interface intellectual property business for $32.5 million in cash, plus additional payments over the next several years, for IP cores, patents and other assets. The strategy behind this acquisition was to meet customer requirements in the server, networking and data center markets.
Rambus, which started its business 25 years ago as a developer of Rambus DRAM technology, announced one year ago it would return to its roots in memory technology innovation by entering the fabless chip business and launching an enhanced-standard DDR4 server memory chipset for RDIMMs and LRDIMMs.
Ferro said the DFI 4.0-compatible R+ DDR4 PHY will enable customers to differentiate their offerings with improved performance while still maintaining full compatibility with industry standard DDR4, and DDR3/3L/3U interfaces. "This gets them ahead of the curve in terms of memory performance," Ferro said.
Ferro said the R+ DDR4 PHY delivers data rates from 800 to 3200 Mbps in multiple memory sub-system options, including die down, DIMM and 3DS. It also supports 16 to 72-bit interfaces, along with single and multi-rank configurations. The goal is to provide flexibility designing systems for both high performance and low power, Ferro said, and that's where the Globalfoundries 14nm process comes in, combined with engineering on the Rambus side.
DDR4 automatically provides 1.5 performance of DDR3, Ferro noted, but the challenge remains: how to improve the interface between the memory and the CPU. “The CPUs can run faster, and they got multiple channels of local DRAM they are accessing, but the CPUs are only as good as the access to the memory," he said. "The interface is the key bottleneck in the system."
Ferro said Rambus is spending a lot of time using internal tools to analyze the physical connections between the CPU and the DIMMs. "That's where the limits come in," he said. "I think there's still a ways to go."
The other challenge is balancing the trade-offs between density and bandwidth by looking at the physical loading onto the bus, Ferro said, and Rambus is looking at technology that minimizes the loading effect of those DIMMs.
—Gary Hilson is a general contributing editor with a focus on memory and flash technologies for EE Times.