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Samsung Debuts 3D XPoint Killer

3D NAND variant stakes out high-end SSDs
8/11/2016 00:01 AM EDT
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Gil Russell
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Re: Kinks and instabilities
Gil Russell   8/13/2016 6:36:00 PM
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Hi Rick,

Z-NAND is based on technology that is in production and is delivering product for revenue - 3D XPoint remains shrouded in mystery. IMFT has taken a big hit in their credibility to execute on schedule. The hole is large enough that it has allowed Samsung to roll out an entirely new product family through it - and almost thanking IMFT for doing such a great job at pioneering the market definition for them. Strategists on both sides of IMFT clearly did not reason the probabilities of this scenario occurring and greatly underestimated Samsung's R&D ability to respond in a timely fashion. 

Samsung's new device has 20 uS balanced R/Ws which is music to the ears of those architecting high performance AFAs and NVDIMM-type Ps for the burgeoning In-Memory Computing market. Byte Addressability might be used by IMFT as a counter argument but the first law of semiconductor memory business; "Price will always be the deciding factor" will take the air out of that argument.

The idea of using a "intelligent" prefetch mechanism to load the on-DIMM DRAM "cache" will further help remove a good deal of latency of the on-DIMM SSD.  This is a near perfect marriage of the new found need for "terabytes" on the memory channel to satisfy the demands of In-Memory Compute Configured servers realizing that a great deal of the initial market uptake consists of an installed base.

Z-NAND is an equal opportunity market share thief operating in a tier where reliably high profit margins still exist. More drama for IDF next week..., 

Ron Neale
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Re: Kinks and instabilities
Ron Neale   8/13/2016 9:31:52 AM
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Resistion: The only problem with drift as far as a 1bit/cell memory like 3DXpoint ™ is concerned would be if drift causes the threshold voltage of the matrix isolation device combined with the drift of the memory device to reach a voltage higher than available on the chip for normal read or write. Other than that it might even be considered by some to be a positive, increasing noise margin of the high resistance state.
I think the real problem for the threshold switch matrix isolation device is the first switching voltage of the as deposited un-switched virgin amorphous material. Experience suggests the first switching voltage will be significantly higher than the normal operating voltage. Perhaps Intel/Micron have found a way of depositing the active material of the matrix isolation device is exactly the same state as it is after it has been threshold switched for the first time.
As I am sure you are aware the reason the memory material is deposited in its crystalline state is to avoid the high first switching voltage.

resistion
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Re: Kinks and instabilities
resistion   8/11/2016 8:43:28 PM
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She said no engineering samples at this stage yet. I thought XPoint measured threshold voltage, so it has to go on. The issue is how much the threshold voltage drifts.

rick merritt
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Re: Kinks and instabilities
rick merritt   8/11/2016 5:42:50 PM
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Great questions, Ron!

I didn't see any media architects at the event who would have been able to field them with authority. I suspect these folks are kept under lock and key ;-)

Maybe I will find the right person at IDF next week.

In the meantime, chime in anyone who knows or has a great guess!

Ron Neale
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Kinks and instabilities
Ron Neale   8/11/2016 1:06:47 PM
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Rick :The phrase "" Getting stable working media is "the gating factor" for the drive"", would appear to be a more refreshing and focussed translation for the 3DXPoint ™ "kinks" you reported in EETimes in January 2016. It would be very interesting to know if these media instabilities relate to the matrix isolation device or the memory. Are the causes of these 3DXpoint instabilities related to the same old PCM problems of element separation or thermal effects, like dissipation, crosstalk and drift or new ones from the matrix isolation device or even the "new recipe memory material? A little more clarity from Intel/Micron on those points would make it a little easier to judge if January 2017 is a reasonable date for their "hopes" to be realised.

The 70/30 read/ write ratio in their demonstration would suggest the threshold switch matrix isolation device is getting quite a pounding, that is if they actually threshold switch it on every read operation.

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