(Image: EE Times)
Two academic projects showed fresh thinking and solid engineering chops from an up-and-coming generation of microprocessor architects including Michael McKeown of Princeton’s Piton project (above).
Piton is a 25-core chip designed as a tile for an array of up to 8,000 chips that can form flexible coherence domains across multiple tiles. “We look toward flattening the data center so communications don’t go through Ethernet or Infiniband but one on-chip interconnect,” said McKeown.
The research chip is based on an OpenSparc T1 core and has been taped out in a 32nm IBM SOI process. At 460 million transistors, it is one of the largest academic chips to date with RTL already available online as open source code.
Separately, students and the University of California at Davis built a 1,000-core chip they claim is the most core-rich device to date. The KiloCore is aimed at work as a co-processor that can be programmed at runtime.
The chip’s novel approach to giving each core micro-tasks handled in a tiny 128-word memory space would no doubt make programming complex. That said, the architecture hits some notable metrics (below) including a potential maximum of 1.78 trillion instructions per second at 40 Watts.
Perhaps even more noteworthy, the young team showed great design dexterity when given just two months’ notice of the opportunity to tape out the design in a 32nm IBM process.
Presenter Brent Bohnenstiehl said he had a “toy processor” available as a starting point that gave him a 20% head start on defining a core. The physical design team had an even shorter window -- they got access to libraries to start their work just 34 days before the fab run.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times