TORONTO—The MRAM market may actually start getting crowded in the next year or so, as another emerging player is looking to commercialize its technology, starting with a sampling program.
Spin Transfer Technologies (STT), developer of Orthogonal Spin Transfer Magneto-Resistive Random Access Memory technology (OST-MRAM), announced today it has fabricated perpendicular MRAM magnetic tunnel junctions (MTJs) as small as 20nm at its development fab based at the company's headquarters in Fremont, Calif.
The company's on-site research and development fab has played a key role in getting to the commercialization stage, said STT CEO Barry Hoberman in a telephone briefing with EE Times, praising STT's ability to process more than 40 wafer lots since the beginning of the year. "To optimize the development cycle time we have built complete clean room for magnetics part of the technology," he added. The next phase is a sampling program that will begin in the first quarter of 2017 with the goal of having STT's MRAM in finished devices in 2018.
MRAM has been an emerging memory technology for some time, with Everspin Technologies being the only vendor shipping commercial product. But despite the limited number of players, Hoberman said MRAM is going into its third generation technology. "pMTJ is where all of the action is right now and that's where we're at."
The company's history can be traced back as far as 2001 with technology was originally developed from research conducted by New York University Professor Andrew Kent. STT was formed and incubated by Boston-based Allied Minds in 2007. To date, it has received $108 million in funding from its investors and has grown to employ 60 people, said Hoberman.
Spin Transfer Technologies is focused on creating favorable performance with respect to the probabilistic aspects of pMTJ MRAM with its proprietary architecture for reading and writing.
He said STT is looking to position itself as the industry best option in terms of speed, power and write endurance by addressing one a key aspect that makes MRAM different from other memories such as DRAM, which is deterministic in its writing, while pMTJ MRAM is probabilistic, so there's certain degree of randomness. Hoberman said that means when you write to a DRAM memory cell a trillion times, you will write good data exactly a trillion times, but with pMTJ, there are few times out of that trillion where data will not write. "The ones that fail to write are random. How you deal with probabilistic behavior is how you achieve performance and reliability."
STT is focused on creating favorable performance with respect to the probabilistic aspects to get more speed, better endurance and lower power with its proprietary architecture for reading and writing, said Hoberman, which enables it to scale to get smaller transistors that translates to lower costs.
Like Everspin, STT sees two streams for MRAM — enterprise storage applications and the embedded market, including automotive and mobile phone display applications, said Hoberman. It will also develop its own standalone MRAM devices while "licensing into foundry food chain." He sees Everspin, STT and a couple of others pioneers on the MRAM, and acknowledges that Everspin has proven there is a viable market. "At least three big foundries have guardedly put MRAM on their roadmap."
Jim Handy, principal analyst with Objective Analysis, said STT is technically behind in the MRAM market, but its ability to do quick on development because they have their own fab is something that could enable them to catch up.
Handy told EE Times that STT's announcement of a sampling program comes at a time where there's been a lot of news about alternative memory technologies thanks to 3D XPoint, as these new technologies are proving to be more than something that could just displace DRAM and NAND flash, as those markets can only be cannibalized if you are faster and cheaper. "With 3D XPoint, Intel said there's a need for a new memory layer."
Handy said there is room for more than MRAM one player to address opportunities including this new memory layer. "One of them needs to execute and if all of them execute it will be mean there are multiple sources," he said. "No one ever likes to use a proprietary memory chip."
—Gary Hilson is a general contributing editor with a focus on memory and flash technologies for EE Times.