LAKE WALES, Fla. — Coventor's SEMulator3D began as a tool for designing microelectromechanical systems (MEMS), then evolved to semiconductor equipment companies, chip makers and foundries for the 3-D structures in FinFETS, 3-D NAND and HD disk-heads. Now every major company in the MEMS and semiconductor supply chain uses Coventor's tools (with over half of their customers making semiconductors instead of MEMS). Next Coventor is anticipating the mixed analog/digital/photonic chips of the future by adding modeling of the optical channels, mixers, and other specialized functions for the coming photonic era.
"Today MEMS and semiconductor makers are grabbing bigger and bigger market shares by using the fabless model, which reduces risk and lowers costs," Mike Jamiolkowski, CEO and President of Coventor told EE Times at the recent MEMS Executive Congress (Scottsdale, Ariz.) "For our MEMS+ tool we offer behavior modeling and a complete library of every major device architecture. For our SEMulator3D tool, which is also used by MEMS makers, we have added libraries of shapes, process integration steps, below-14-nanometer architectures, prefab device structures, and virtual fabrication capabilities for FinFETs, 3-D NANDs, hard disk (HD heads and other nanoscale applications. Now by adding photonic device libraries, SEMulator3D can offer faster/smaller dies, higher yields and multi-variable analysis for MEMS, semiconductors and photonic devices too."
Silicon photonics test die with top cladding removed to show structures, with close-ups of a (a) Mach-Zehnder modulator and (b) directional coupler
Virtual fabrication likewise allows a MEMS, semiconductor, photonic and mixed-signal chip-makers to find and correct flaws before the first tape-out, saving time and wafer costs. Now Coventor is extending their analytics to virtual wafer fabrication which goes beyond yield and variability analytics to identify troublesome process variables, deposition sizes, mask alignment problems and the feasibility of using extreme ultra-violet (EUV) for some of the critical patterning steps. In the process, Coventor has invented a new buzz-word "patterning budget" which will allow MEMS, semiconductor, photonic and mixed signal chip makers to determine where using EUV will be profitable to do so and where convention immersion lithography should be used in the fabrication of the same chip.
Coventor is collaborating with the Massachusetts Institute of Technology (MIT) and the AIM Photonics program to which it belongs on silicon photonics expertise building.
— R. Colin Johnson, Advanced Technology Editor, EE Times