LAKE WALES, Fla. — Photonics may be the future of the post-Moore's Law era, with electronic design automation (EDA) tools already available to make the transition. Now IMEC research institute (Leuven, Belgium) claims that it has demonstrated sub-micron spin-wave devices (SWDs) integrated with state-of-the-art FinFETs, announcing it this month at the Annual Conference on Magnetism and Magnetic Materials 2016.
Thus, the transition "beyond CMOS" to the 100 billion times smaller world of photonics begins.
The world's first sub-micron spin-wave majority gate with sub-micron spacing of just 88 nanometers.
"There are few options targeting very-low-power operation in these devices," Iuliana Radu, distinguished member of technical staff coordinating "Beyond CMOS" at IMEC, told EE Times. "IMEC has reported the first design of a working majority gate device based on spin waves based on detailed micro-magnetic simulations.
"The only other set of devices targeting the same low-power space are the tunneling FETs, which have their own set of challenges. It’s not clear which of these devices will make it in the end. IMEC is working on both approaches. Potential advantage of spin-wave majority gates compared to transistors, including the tunneling FET, is that photonic devices could be lower in energy per operation, integrate with non-volatile elements, and efficiently be implemented for functional scaling. In this context, functional scaling means that same-circuit functionality can be implemented with fewer devices than CMOS."
First-generation integration of two spin-wave devices (top, right, and left) with 3D FinFETs (middle) on doped silicon substrate (bottom).
The transition has already begun with silicon photonics, with Intel and many others already using silicon optical transceivers on-chip to speed the connection among multiple cores. With the integration of photonics with FinFETS (see second figure) the transition from electronics to photonics should be smooth.
"We expect these devices to be commercialized over a 10+ year horizon," Radu told EE Times.
The major remaining engineering hurdles, besides optimization, is the familiarization of designers with using a "majority gate" model for designing circuitry instead of the NAND gate philosophy of electronics. But the hugest hurdle is convincing the foundries to make the investment in time to make use of the new photonic materials. Process engineers will do everything possible to avoid the use of new materials and will have to be convinced that photonics is worth the trouble.
Gate areas and designs for spin-wave device technology with distances parameterized for the wavelength of the spin wave.
Photonic "devices use majority gates, whereas standard tools for electronic circuit synthesis use NAND operations. Simple tools to use majority gates rather than NAND are available, but for industrial commercialization, deeper refinement and optimization are needed," Radu told us. "The hugest hurdle is to bring the materials needed for these photonic devices into a CMOS fab. IMEC, together with our partners and collaborators, have started groundbreaking work in this direction. The time for new materials adoption is very long as many experimental details need to be addressed. IMEC has reported work toward the understanding of the materials [at Magnetism and Magnetic Materials 2016]. And last, but not least, device reliability could be one of the possible show-stoppers as little is known how some of these materials — piezoelectrics for example — will behave under the stringent requirements of a logic circuit."
Get all of the details in System-level assessment and area evaluation of spin wave logic circuits
— R. Colin Johnson, Advanced Technology Editor, EE Times